The A20 has EMAC and GMAC muxed on the same pins.
Add pin sets with gmac function for MII and RGMII mode to the DTSI.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The GMAC uses 1 of 2 sources for its transmit clock, depending on the
PHY interface mode. Add both sources as dummy clocks, and as parents
to the GMAC clock node.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The clkc has its registers in the range of the slcr.
Instead of passing around the slcr base address pointer, let the clkc get the
address from the DT.
This prepares the slcr to be a real driver with multiple memory ranges
(slcr, clocks, pinctrl,...)
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Split the slcr into an early part for unlocking and cpu starting
and a later syscon driver.
Also add "syscon" compatible property for slcr.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Apply the same work-around for i.MX 6D/Q erratum 006687 as used for
Sabre Lite for the Wandboard Dual / Quad.
Like on the Sabre Lite, GPIO6 is used as a power down output for
camera expansion boards. However, these expansion boards do not work
with mainline yet anyway.
Tested on a Wandboard Quad. Before the patch:
root@arm:~# ping -q -f -c 10000 192.168.2.1
PING 192.168.2.1 (192.168.2.1) 56(84) bytes of data.
=== 192.168.2.1 ping statistics ===
10000 packets transmitted, 10000 received, 0% packet loss, time 97363ms
rtt min/avg/max/mdev = 0.290/9.586/10.198/1.432 ms, pipe 2, ipg/ewma 9.737/9.672 ms
After the patch:
root@arm:~# ping -q -f -c 10000 192.168.2.1
PING 192.168.2.1 (192.168.2.1) 56(84) bytes of data.
=== 192.168.2.1 ping statistics ===
10000 packets transmitted, 10000 received, 0% packet loss, time 4810ms
rtt min/avg/max/mdev = 0.246/0.355/0.863/0.044 ms, ipg/ewma 0.481/0.319 ms
Signed-off-by: Sascha Silbe <x-linux@infra-silbe.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
From schematic, the power, vol+/- key's active state is low,
so we need to set the gpio flag to active low.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add support for the GK802 'QUAD CORE Mini PC', which seems to be loosely
based on the Freescale i.MX6Q HDMI dongle reference design.
It is supposedly identical to the Hiapad Hi802.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The DFI FS700-M60 is a q7 board with i.MX6 quad, dual, duallite or solo
SoC. This adds support for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
imx51-ssi and imx21-ssi are different IPs. imx51-ssi supports online
reconfiguration and needs this for correct interaction with SDMA. This
patch adds imx51-ssi before each imx21-ssi for all imx6 SoCs.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The quad version has a SPI controller more than the other
versions. Add an alias for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We need to use controller id to access different register regions
for mxs phy.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This works around a hardware bug.
From "Chip Errata for the i.MX 6Dual/6Quad"
ERR006687 ENET: Only the ENET wake-up interrupt request can wake the
system from Wait mode.
The ENET block generates many interrupts. Only one of these interrupt lines
is connected to the General Power Controller (GPC) block, but a logical OR
of all of the ENET interrupts is connected to the General Interrupt Controller
(GIC). When the system enters Wait mode, a normal RX Done or TX Done does not
wake up the system because the GPC cannot see this interrupt. This impacts
performance of the ENET block because its interrupts are serviced only when
the chip exits Wait mode due to an interrupt from some other wake-up source.
Before this patch, ping times of a Sabre Lite board are quite
random:
ping 192.168.0.13 -i.5 -c5
PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data.
64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=15.7 ms
64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=14.4 ms
64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=13.4 ms
64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=12.4 ms
64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=11.4 ms
=== 192.168.0.13 ping statistics ===
5 packets transmitted, 5 received, 0% packet loss, time 2004ms
rtt min/avg/max/mdev = 11.431/13.501/15.746/1.508 ms
____________________________________________________
After this patch:
ping 192.168.0.13 -i.5 -c5
PING 192.168.0.13 (192.168.0.13) 56(84) bytes of data.
64 bytes from 192.168.0.13: icmp_req=1 ttl=64 time=0.120 ms
64 bytes from 192.168.0.13: icmp_req=2 ttl=64 time=0.175 ms
64 bytes from 192.168.0.13: icmp_req=3 ttl=64 time=0.169 ms
64 bytes from 192.168.0.13: icmp_req=4 ttl=64 time=0.168 ms
64 bytes from 192.168.0.13: icmp_req=5 ttl=64 time=0.172 ms
=== 192.168.0.13 ping statistics ===
5 packets transmitted, 5 received, 0% packet loss, time 1999ms
rtt min/avg/max/mdev = 0.120/0.160/0.175/0.026 ms
____________________________________________________
Also, apply same change to imx6qdl-nitrogen6x.
This change may not be appropriate for all boards.
Sabre Lite uses GPIO6 as a power down output for a ov5642
camera. As this expansion board does not yet work with mainline,
this is not yet a conflict. It would be nice to have an alternative
fix for boards where this is a problem.
For example Sabre SD uses GPIO6 for I2C3_SDA. It also
has long ping times currently. But cannot use this fix
without giving up a touchscreen.
Its ping times are also random.
ping 192.168.0.19 -i.5 -c5
PING 192.168.0.19 (192.168.0.19) 56(84) bytes of data.
64 bytes from 192.168.0.19: icmp_req=1 ttl=64 time=16.0 ms
64 bytes from 192.168.0.19: icmp_req=2 ttl=64 time=15.4 ms
64 bytes from 192.168.0.19: icmp_req=3 ttl=64 time=14.4 ms
64 bytes from 192.168.0.19: icmp_req=4 ttl=64 time=13.4 ms
64 bytes from 192.168.0.19: icmp_req=5 ttl=64 time=12.4 ms
=== 192.168.0.19 ping statistics ---
5 packets transmitted, 5 received, 0% packet loss, time 2003ms
rtt min/avg/max/mdev = 12.451/14.369/16.057/1.316 ms
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Ranjani Vaidyanathan <ra5478@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The D25 LED controlled by gpio on the i.MX51 babbage
board is a diagnostic LED according to the board design.
This patch adds the relevant device tree nodes to the
i.MX51 babbage device tree file to support this LED.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
'enable-active-low' is not a valid property for a GPIO controlled regulator.
According to Documentation/devicetree/bindings/regulator/gpio-regulator.txt:
"Optional properties:
...
- enable-active-high : Polarity of GPIO is active high (default is low)."
,so the correct way to define an active-low GPIO controlled regulator is to
simply not pass 'enable-active-high'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
'enable-active-low' is not a valid property for a GPIO controlled regulator.
According to Documentation/devicetree/bindings/regulator/gpio-regulator.txt:
"Optional properties:
...
- enable-active-high : Polarity of GPIO is active high (default is low)."
,so the correct way to define an active-low GPIO controlled regulator is to
simply not pass 'enable-active-high'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
imx51-ssi and imx21-ssi are different IPs. imx51-ssi supports online
reconfiguration and needs this for correct interaction with SDMA. This
patch adds imx51-ssi before each imx21-ssi for all imx5 SoCs.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds support for the Ka-Ro electronics GmbH TX53 modules.
There are two distinct module types. One with an LVDS display
interface and SATA support, the other with a parallel LCD
interface and no SATA interface.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The "Start-R QSB" has a different PMIC than the older "Start QSB".
Add a new devicetree for the Start-R.
They both could use the same DT, as both PMICs (the dialog and the mc34708)
have different i2c addresses and could coexist in the same DT without any
errors. But once phandles are used, this will get messy.
The pmic nodes are based on an earlier patch
[PATCH] arm: imx53-qsb: Add Ripley driver DT nodes
from
Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
which apparently got lost/abandoned.
I added phandles/newlines and changed the node name from ripley to mc34708.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
There are (atleast) two versions of the i.MX53 LOCO:
- the MCIMX53-START board
- the MCIMX53-START-R board
The MCIMX53-START-R has a mc34708 pmic and is otherwise the similar to the
MCIMX53-START. To prepare for the START-R, move all common nodes to a new
imx53-qsb-common.dtsi and remove everything but the board name and pmic from
the imx53-qsb.dts.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
imx53-evk board is discontinued by Freescale. The replacement is
imx53-qsb. Additionally this board is not supported by anyone and
in their current state is non-functional, for example PMIC not have
an IRQ line defined, so it is not works. This patch removes this DTS.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch uses the IRQ_TYPE_LEVEL_HIGH/IRQ_TYPE_NONE to replace
the hardcode.
[shawn.guo: While at it, we also fix the typo in uart0 interrupts
property, where the 0x00 should 0x04. Hense, it should also be
IRQ_TYPE_LEVEL_HIGH just like other UART instances.]
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds the missing (Synchronous Serial Interface) SSI1 & SSI2
devicetree nodes for i.MX27 CPUs.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We need to use controller id to access different register regions
for mxs phy.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds pinctrl definitions for WEIM CS4 and GPIO used as
CAN IRQ line.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Since SPI core does not use GPIO bindings for CS GPIOs,
we should add an active high level declaration.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
