5 Commits

Author	SHA1	Message	Date
Thomas Langer	362b34faef	MIPS: Lantiq: Falcon: add cpu-feature-override.h ... Add cpu-feature-override.h for the GPON SoC Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5658/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>	2013-09-03 23:22:16 +02:00
Ralf Baechle	7034228792	MIPS: Whitespace cleanup. ... Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>	2013-02-01 10:00:22 +01:00
John Crispin	e316cb2b16	OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC ... Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks of up to 32 pins. Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org	2012-09-13 10:30:58 +02:00
John Crispin	61fa969f27	MIPS: lantiq: split up IRQ IM ranges ... Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate the SVIP we need to support IM ranges that are scattered inside the register range. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4237/	2012-08-23 00:08:17 +02:00
John Crispin	d41ced01f2	MIPS: lantiq: implement support for FALCON soc ... Adds support for the FALCON SoC. This SoC is from the FTTH/GPON SoC family. Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3814/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>	2012-05-21 14:31:55 +01:00