this patch adds lost ethernet gmac node, and also fix the ranges of
its parent node.
Signed-off-by: Ye He <ye.he@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
this patch adds lost jpeg node, and also fix the ranges of its
parent node.
Signed-off-by: Lily.Li <Lily.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Add FEC MAC refrence clock init.
Add phy fixup init for i.MX6ul 14x14 evk board that installs KSZ8081 phy.
For the phy, there needs extra phy fixup for MII and RMII mode.
Signed-off-by: Fugang Duan <b38611@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add eMMC pinmux and mmc2 related bits. We keep the mmc2
controller disabled as it conflits with gpmc/NAND.
To enable emmc, simply set mmc2 controller node to "okay"
and set the gpmc node to "disabled" and change the
SelEMMCorNAND gpio-hog to output-high.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On this board either eMMC or NAND can work based on the level of
spi2_cs0.gpio0_23. Add a gpio-hog to enable configuration of this
pin in the device tree.
Move pinmux for spi2_cs0 (SEL_eMMCorNANDn) out of
NAND node into gpio0 so it is initialized with gpio0.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ldo1_reg in addition to being connected to the io lines is also
connected to the card detect line. On card removal, omap_hsmmc
driver does a regulator_disable causing card detect line to be
pulled down. This raises a card insertion interrupt and once the
MMC core detects there is no card inserted, it does a
regulator disable which again raises a card insertion interrupt.
This happens in a loop causing infinite MMC interrupts.
Fix it by making ldo1_reg as always_on.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ldo1_reg in addition to being connected to the io lines is also
connected to the card detect line. On card removal, omap_hsmmc
driver does a regulator_disable causing card detect line to be
pulled down. This raises a card insertion interrupt and once the
MMC core detects there is no card inserted, it does a
regulator disable which again raises a card insertion interrupt.
This happens in a loop causing infinite MMC interrupts.
Fix it by making ldo1_reg as always_on.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
pbias-supply is initialized in dra7.dtsi. Remove redundant initialization
of pbias-supply from MMC1 dt node in am57xx-beagle-x15.dts
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
SDMMC Card Detect can be used over default GPIO map.
Reported-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
MMC1 supports SDR104 and MMC2 supports HS200 both of which requires
192MHz clock. Set the maximum operating clock frequency to 192 MHz.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a node for evm_3v3_sd using onboard pcf GPIO expander which feeds
on to mmc vdd.
Update mapping for vmmc-supply and vmmc_aux-supply.
evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines.
Signed-off-by: Balaji T K <balajitk@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add a node for evm_3v3_sd using pcf which feeds on to mmc vdd.
Update mapping for vmmc-supply and vmmc_aux-supply.
evm_3v3_sd supplies to SD card vdd, and ldo1 to sdcard i/o lines.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The logic used to check ept misconfig is completely contained in common
reserved bits check for sptes, so it can be removed
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The #PF with PFEC.RSV = 1 is designed to speed MMIO emulation, however,
it is possible that the RSV #PF is caused by real BUG by mis-configure
shadow page table entries
This patch enables full check for the zero bits on shadow page table
entries (which includes not only bits reserved by the hardware, but also
bits that will never be set in the SPTE), then dump the shadow page table
hierarchy.
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
We have the same data struct to check reserved bits on guest page tables
and shadow page tables, split is_rsvd_bits_set() so that the logic can be
shared between these two paths
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
We have abstracted the data struct and functions which are used to check
reserved bit on guest page tables, now we extend the logic to check
zero bits on shadow page tables
The zero bits on sptes include not only reserved bits on hardware but also
the bits that SPTEs willnever use. For example, shadow pages will never
use GB pages unless the guest uses them too.
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Since shadow ept page tables and Intel nested guest page tables have the
same format, split reset_rsvds_bits_mask_ept so that the logic can be
reused by later patches which check zero bits on sptes
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Since softmmu & AMD nested shadow page tables and guest page tables have
the same format, split reset_rsvds_bits_mask so that the logic can be
reused by later patches which check zero bits on sptes
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
These two fields, rsvd_bits_mask and bad_mt_xwr, in "struct kvm_mmu" are
used to check if reserved bits set on guest ptes, move them to a data
struct so that the approach can be applied to check host shadow page
table entries as well
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
FNAME(is_rsvd_bits_set) does not depend on guest mmu mode, move it
to mmu.c to stop being compiled multiple times
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
We got the bug that qemu complained with "KVM: unknown exit, hardware
reason 31" and KVM shown these info:
[84245.284948] EPT: Misconfiguration.
[84245.285056] EPT: GPA: 0xfeda848
[84245.285154] ept_misconfig_inspect_spte: spte 0x5eaef50107 level 4
[84245.285344] ept_misconfig_inspect_spte: spte 0x5f5fadc107 level 3
[84245.285532] ept_misconfig_inspect_spte: spte 0x5141d18107 level 2
[84245.285723] ept_misconfig_inspect_spte: spte 0x52e40dad77 level 1
This is because we got a mmio #PF and the handler see the mmio spte becomes
normal (points to the ram page)
However, this is valid after introducing fast mmio spte invalidation which
increases the generation-number instead of zapping mmio sptes, a example
is as follows:
1. QEMU drops mmio region by adding a new memslot
2. invalidate all mmio sptes
3.
VCPU 0 VCPU 1
access the invalid mmio spte
access the region originally was MMIO before
set the spte to the normal ram map
mmio #PF
check the spte and see it becomes normal ram mapping !!!
This patch fixes the bug just by dropping the check in mmio handler, it's
good for backport. Full check will be introduced in later patches
Reported-by: Pavel Shirshov <ru.pchel@gmail.com>
Tested-by: Pavel Shirshov <ru.pchel@gmail.com>
Signed-off-by: Xiao Guangrong <guangrong.xiao@linux.intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Add the Wakeup M3 IPC device node for the wkup_m3_ipc driver on
AM4372 SoC. This node uses the IPC registers, part of the Control
Module, and is therefore added as a child of the scm node.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the Wakeup M3 IPC node for the wkup_m3_ipc driver on AM33xx SoCs.
This node uses the IPC registers, part of the Control Module, and is
therefore added as a child of the scm node.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
commit <d919501feffa> ("ARM: dts: dra7: add minimal l4 bus
layout with control module support") moved pbias_regulator dt node
from being a child node of ocp to be the child node of
scm_conf. After this device for pbias_regulator is
not created.
Fix it by adding "simple-bus" compatible property to
scm_conf dt node.
Fixes: d919501fef ("ARM: dts: dra7: add minimal l4 bus
layout with control module support")
Cc: <stable@vger.kernel.org> # v4.1
Suggested-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
commit <ed8509edddeb> ("ARM: dts: omap5: add minimal l4 bus
layout with control module support") moved pbias_regulator dt node
from being a child node of ocp to be the child node of
omap5_padconf_global. After this device for pbias_regulator is
not created.
Fix it by adding "simple-bus" compatible property to
omap5_padconf_global dt node.
Fixes: ed8509eddd ("ARM: dts: omap5: add minimal l4 bus
layout with control module support")
Cc: <stable@vger.kernel.org> # v4.1
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
commit <7415b0b4c645> ("ARM: dts: omap4: add minimal l4 bus layout
with control module support") moved pbias_regulator dt node
from being a child node of ocp to be the child node of
omap4_padconf_global. After this device for pbias_regulator
is not created.
Fix it by adding "simple-bus" compatible property to
omap4_padconf_global dt node.
Fixes: 7415b0b4c6 ("ARM: dts: omap4: add minimal l4 bus layout
with control module support")
Cc: <stable@vger.kernel.org> # v4.1
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
commit <72b10ac00eb1> ("ARM: dts: omap24xx: add minimal l4 bus
layout with control module support") moved pbias_regulator dt node
from being a child node of ocp to be the child node of
scm_conf. After this device for pbias_regulator is
not created.
Fix it by adding "simple-bus" compatible property to
scm_conf dt node.
Fixes: 72b10ac00e ("ARM: dts: omap24xx: add minimal l4 bus
layout with control module support")
Cc: <stable@vger.kernel.org> # v4.1
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This region contains CTRL_CORE_SMA_SW2..9 registers which
are not specific to any domain and can be reasonably
accessed via syscon driver.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
We need to add 4 bytes to include the last 32-bit register space.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
These nodes are wrongly placed. They must come under the
scm node. Nobody uses them either so get rid of them.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit 60f96b41f7 ("genirq: Add IRQCHIP_SKIP_SET_WAKE flag")
introduced a new flag to skip the irq_set_wake callback in the irqchip
core to avoid adding dummy irq_set_wake in the irqchip implementations.
This patch removes the dummy callback and sets the IRQCHIP_SKIP_SET_WAKE
flags.
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
mvebu config changes for v4.3 (part #2)
Improve dt support for orion5x
* tag 'mvebu-config-4.3-2' of git://git.infradead.org/linux-mvebu:
ARM: defconfig: orion5x: add DT support
Signed-off-by: Olof Johansson <olof@lixom.net>
On MIPS the GLOBAL bit of the PTE must have the same value in any
aligned pair of PTEs. These pairs of PTEs are referred to as
"buddies". In a SMP system is is possible for two CPUs to be calling
set_pte() on adjacent PTEs at the same time. There is a race between
setting the PTE and a different CPU setting the GLOBAL bit in its
buddy PTE.
This race can be observed when multiple CPUs are executing
vmap()/vfree() at the same time.
Make setting the buddy PTE's GLOBAL bit an atomic operation to close
the race condition.
The case of CONFIG_64BIT_PHYS_ADDR && CONFIG_CPU_MIPS32 is *not*
handled.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: <stable@vger.kernel.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10835/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
mvebu soc changes for v4.3 (part #1)
- Extend suspend to RAM support in order to add new mvebu SoC
- Add standby support for all Armada 3xx/XP SoCs
* tag 'mvebu-soc-4.3-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Warn about the wake-up sources not taken into account in suspend
ARM: mvebu: Add standby support
ARM: mvebu: Use __init for the PM initialization functions
ARM: mvebu: prepare pm-board.c for the introduction of Armada 38x support
ARM: mvebu: prepare mvebu_pm_store_bootinfo() to support multiple SoCs
ARM: mvebu: do not check machine in mvebu_pm_init()
ARM: mvebu: prepare set_cpu_coherent() for future extension
Signed-off-by: Olof Johansson <olof@lixom.net>
The arm64 booting document requires that the bootloader has cleaned the
kernel image to the PoC. However, when a CPU re-enters the kernel due to
either a CPU hotplug "on" event or resuming from a low-power state (e.g.
cpuidle), the kernel text may in-fact be dirty at the PoU due to things
like alternative patching or even module loading.
Thanks to I-cache speculation with the MMU off, stale instructions could
be fetched prior to enabling the MMU, potentially leading to crashes
when executing regions of code that have been modified at runtime.
This patch addresses the issue by ensuring that the local I-cache is
invalidated immediately after a CPU has enabled its MMU but before
jumping out of the identity mapping. Any stale instructions fetched from
the PoC will then be discarded and refetched correctly from the PoU.
Patching kernel text executed prior to the MMU being enabled is
prohibited, so the early entry code will always be clean.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The asm audit optimizations are ugly and obfuscate the code too
much. Remove them.
This will regress performance if syscall auditing is enabled on
32-bit kernels and SYSENTER is in use. If this becomes a
problem, interested parties are encouraged to implement the
equivalent of the 64-bit opportunistic SYSRET optimization.
Alternatively, a case could be made that, on 32-bit kernels, a
less messy asm audit optimization could be done. 32-bit kernels
don't have the complicated partial register saving tricks that
64-bit kernels have, so the SYSENTER post-syscall path could
just call the audit hooks directly. Any reimplementation of
this ought to demonstrate that it only calls the audit hook once
per syscall, though, which does not currently appear to be true.
Someone would have to make the case that doing so would be
better than implementing opportunistic SYSEXIT, though.
Signed-off-by: Andy Lutomirski <luto@kernel.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Eric Paris <eparis@parisplace.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Link: http://lkml.kernel.org/r/212be39dd8c90b44c4b7bbc678128d6b88bdb9912.1438378274.git.luto@kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arm: Xilinx Zynq SoC patches for v4.2
- Fix earlyprintk, jump trampoline for SMP
- Update git tree location
- Setup PL310 aux (bit 22)
* tag 'zynq-soc-for-4.3' of https://github.com/Xilinx/linux-xlnx:
ARM: zynq: reserve space for jump target in secondary trampoline
clk: zynq: remove redundant $(CONFIG_ARCH_ZYNQ) in Makefile
MAINTAINERS: Update Zynq git tree location
ARM: zynq: Set bit 22 in PL310 AuxCtrl register (6395/1)
ARM: zynq: Fix earlyprintk in big endian mode
Signed-off-by: Olof Johansson <olof@lixom.net>
Qualcomm ARM Based defconfig Updates for v4.3
* Enable KS8851 for QCOM SoCs in qcom defconfig
* tag 'qcom-defconfig-for-4.3' of git://codeaurora.org/quic/kernel/agross-msm:
ARM: qcom_defconfig: Enable options for KS8851 ethernet
Signed-off-by: Olof Johansson <olof@lixom.net>
Qualcomm ARM Based Device Tree Updates for v4.3
* Switch to use pinctrl compatible for GPIOs
* Add RPM regulators for MSM8960
* Add SPI Ethernet support on MSM8960 CDP
* Add SMEM support along with dependencies
* Add PM8921 support for GPIO and MPP
* Fix GSBI cell index
* Switch to use real regulators on APQ8064 w/ SDCC
* tag 'qcom-dt-for-4.3' of git://codeaurora.org/quic/kernel/agross-msm:
ARM: dts: qs600: Add real regulators to sdcc
ARM: dts: ifc6410: add real regulators for sdcc nodes.
ARM: dts: apq8064: remove temporary fixed regulator for mmc
ARM: dts: apq8064: fix missing gsbi cell-index
ARM: dts: apq8064: Add DT support for GSBI6 and for UART pin mux
ARM: dts: apq8064: add pm8921 mpp support
ARM: dts: apq8064: Add pm8921 mfd and its gpio node
ARM: dts: msm8974: Add smem reservation and node
ARM: dts: msm8974: Add tcsr mutex node
ARM: dts: qcom: Add ks8851 node for wired ethernet
ARM: dts: qcom: Add MSM8960 CDP RPM regulators
ARM: dts: qcom: Add MSM8960 RPM and RPM regulator nodes
ARM: dts: qcom: Replace gpio node with pinctrl node
ARM: dts: qcom: Replace gpio node with pinctrl node
Signed-off-by: Olof Johansson <olof@lixom.net>
Add Atmel-isi and ov2640 driver in defconfig
Signed-off-by: Josh Wu <josh.wu@atmel.com>
[nicolas.ferre@atmel.com: make SOC_CAMERA_OV2640 selected as a module]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
