this patch is againest v4.2-rc1, by doing:
$ make ARCH=arm prima2_defconfig
$ make ARCH=arm savedefconfig
$ cp defconfig arch/arm/configs/prima2_defconfig
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Other serial driver work wants to build on patches now in 4.2-rc4 so
merge the branch so this can properly happen.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
lib/list_sort.c defines a 'struct debug_el', where "el" is assumedly a
a contraction of "element". This conflicts with 'enum debug_el' in our
asm/debug-monitors.h header file, where "el" stands for Exception Level.
The result is build failure when targetting allmodconfig, so rename our
enum to 'dbg_active_el' to be slightly more explicit about what it is.
Signed-off-by: Will Deacon <will.deacon@arm.com>
It is not needed after booting, this patch moves the
free_initrd_mem() function to the __init section.
This patch also make keep_initrd __initdata, to reduce kernel
size.
Signed-off-by: Wang Long <long.wanglong@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
At boot, the UTF-16 UEFI vendor string is copied from the system
table into a char array with a size of 100 bytes. However, this
size of 100 bytes is also used for memremapping() the source,
which may not be sufficient if the vendor string exceeds 50
UTF-16 characters, and the placement of the vendor string inside
a 4 KB page happens to leave the end unmapped.
So use the correct '100 * sizeof(efi_char16_t)' for the size of
the mapping.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Fixes: f84d02755f ("arm64: add EFI runtime services")
Cc: <stable@vger.kernel.org> # 3.16+
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
cpuid_feature_extract_field takes care of the fiddly ID register
field sign-extension, so use that instead of rolling our own version.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Rework the cpufeature detection to support ISAR0 and use that for
detecting the presence of LSE atomics.
Signed-off-by: Will Deacon <will.deacon@arm.com>
ARMv8 CPUs do not support any of the v8.1 features, so group them
together in Kconfig to make it clear that they're part of 8.1 and not
relevant to older cores.
Signed-off-by: Will Deacon <will.deacon@arm.com>
It is useful to know how the kernel was configured via:
zcat /proc/config.gz ,so select the CONFIG_IKCONFIG_PROC option.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
If we attempt to atomic64_dec_if_positive on INT_MIN, we will underflow
and incorrectly decide that the original parameter was positive.
This patches fixes the broken condition code so that we handle this
corner case correctly.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
We don't need duplicate cmpxchg implementations, so use cmpxchg to
implement atomic{,64}_cmpxchg, like we do for xchg already.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The cost of changing a cacheline from shared to exclusive state can be
significant, especially when this is triggered by an exclusive store,
since it may result in having to retry the transaction.
This patch makes use of prfm to prefetch cachelines for write prior to
ldxr/stxr loops when using the ll/sc atomic routines.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The common (i.e. identical for ll/sc and lse) atomic macros in atomic.h
are needlessley different for atomic_t and atomic64_t.
This patch tidies up the definitions to make them consistent across the
two atomic types and factors out common code such as the add_unless
implementation based on cmpxchg.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
cmpxchg doesn't require memory barrier semantics when the value
comparison fails, so make the barrier conditional on success.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
We can perform the cmpxchg comparison using eor and cbnz which avoids
the "cc" clobber for the ll/sc case and consequently for the LSE case
where we may have to fall-back on the ll/sc code at runtime.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
On CPUs which support the LSE atomic instructions introduced in ARMv8.1,
it makes sense to use them in preference to ll/sc sequences.
This patch introduces runtime patching of our cmpxchg_double primitives
so that the LSE casp instruction is used instead.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
On CPUs which support the LSE atomic instructions introduced in ARMv8.1,
it makes sense to use them in preference to ll/sc sequences.
This patch introduces runtime patching of our cmpxchg primitives so that
the LSE cas instruction is used instead.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
On CPUs which support the LSE atomic instructions introduced in ARMv8.1,
it makes sense to use them in preference to ll/sc sequences.
This patch introduces runtime patching of our xchg primitives so that
the LSE swp instruction (yes, you read right!) is used instead.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
On CPUs which support the LSE atomic instructions introduced in ARMv8.1,
it makes sense to use them in preference to ll/sc sequences.
This patch introduces runtime patching of our bitops functions so that
LSE atomic instructions are used instead.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
On CPUs which support the LSE atomic instructions introduced in ARMv8.1,
it makes sense to use them in preference to ll/sc sequences.
This patch introduces runtime patching of our locking functions so that
LSE atomic instructions are used for spinlocks and rwlocks.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
On CPUs which support the LSE atomic instructions introduced in ARMv8.1,
it makes sense to use them in preference to ll/sc sequences.
This patch introduces runtime patching of atomic_t and atomic64_t
routines so that the call-site for the out-of-line ll/sc sequences is
patched with an LSE atomic instruction when we detect that
the CPU supports it.
If binutils is not recent enough to assemble the LSE instructions, then
the ll/sc sequences are inlined as though CONFIG_ARM64_LSE_ATOMICS=n.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
In order to patch in the new atomic instructions at runtime, we need to
generate wrappers around the out-of-line exclusive load/store atomics.
This patch adds a new Kconfig option, CONFIG_ARM64_LSE_ATOMICS. which
causes our atomic functions to branch to the out-of-line ll/sc
implementations. To avoid the register spill overhead of the PCS, the
out-of-line functions are compiled with specific compiler flags to
force out-of-line save/restore of any registers that are usually
caller-saved.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Add a CPU feature for the LSE atomic instructions, so that they can be
patched in at runtime when we detect that they are supported.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
The ARM v8.1 architecture introduces new atomic instructions to the A64
instruction set for things like cmpxchg, so advertise their availability
to userspace using a hwcap.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
In preparation for the Large System Extension (LSE) atomic instructions
introduced by ARM v8.1, move the current exclusive load/store (LL/SC)
atomics into their own header file.
Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
cpufeature.h makes use of DECLARE_BITMAP, which in turn relies on the
BITS_TO_LONGS and DIV_ROUND_UP macros.
This patch includes kernel.h in cpufeature.h to prevent all users having
to do the same thing.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
STXR can fail for a number of reasons, so don't fail an rwlock trylock
operation simply because the STXR reported failure.
I'm not aware of any issues with the current code, but this makes it
consistent with spin_trylock and also other architectures (e.g. arch/arm).
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
This gets the GPIO ranges out of the driver and into the device
tree where they belong. Standard DT bindings already exist for
this. Since no systems with this are deployed we can just augment
all device trees and the drivers at the same time and simplify
the world.
This also defines the array of GPIO chips related to the pin
controller.
Cc: arm@kernel.org
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The DT nodes in uniphier-pinctrl.dtsi provide the default pinctrl
settings that would be suitable for most boards. You can still
override them in your board DTS file if necessary.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the pinctrol device nodes for UniPhier PH1-LD4, PH1-Pro4,
and PH1-sLD8.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
This is the pxa changes for v4.3 cycle.
There is mostly one evolution on the dma side, to enable cooperation
of the legacy pxa DMA API, and the new dmaengine API.
Once all drivers using DMA are converted, the legacy DMA API should
be removed.
* tag 'pxa-for-4.3-v2' of https://github.com/rjarzmik/linux:
ARM: pxa: Use setup_timer
ARM: pxa: Use module_platform_driver
ARM: pxa: transition to dmaengine phase 1
Signed-off-by: Olof Johansson <olof@lixom.net>
omap dts changes for minimal dm814x support for v4.3 merge window.
These changes make dm814x boot and adds minimal board support for
dm814x-evm and hp t410.
Note that to boot these depend on omap-for-v4.3/soc-signed branch,
but as dm814x support is currently broken, these can be merged
separately with the other dts changes.
* tag 'omap-for-v4.3/dt-dm814x' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Add custom abort handler for t410
ARM: dts: Add minimal support for HP T410
ARM: dts: Add minimal dts support for dm8148-evm
ARM: dts: Add minimal clocks for dm814x
ARM: dts: Add minimal dm814x support
Signed-off-by: Olof Johansson <olof@lixom.net>
SoC changes for omaps for v4.3 merge window:
- Clean-up omap4_local_timer_init to drop deal legacy code
- Provide proper IO map table for dra7
- Clean-up IOMMU layer init code as it now uses IOMMU framework
- A series of changes to fix up dm814x support that's been in a broken
half-merged state for quite some time
- A series of PRCM and hwmod changes via Paul Walmsley <paul@pwsan.com>:
- I/O wakeup support for AM43xx
- register lock and unlock support to the hwmod code (needed for the RTC
IP blocks on some chips)
- several fixes for sparse warnings and an unnecessary null pointer test
- a DRA7xx clockdomain configuration workaround, to deal with some hardware
bugs
* tag 'omap-for-v4.3/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits)
ARM: OMAP2: Add minimal dm814x hwmod support
ARM: OMAP2+: Prepare dm81xx hwmod code for adding minimal dm814x support
ARM: PRM: AM437x: Enable IO wakeup feature
ARM: OMAP4+: PRM: Add AM437x specific data
ARM: OMAP: PRM: Remove hardcoding of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 register offsets
ARM: dts: AM4372: Add PRCM IRQ entry
ARM: AM43xx: Add the PRM IRQ register offsets
ARM: OMAP4: PRM: Remove hardcoding of PRM_IO_PMCTRL_OFFSET register
ARM: OMAP2+: Add support for initializing dm814x clocks
ARM: OMAP2+: Add custom prwdm_operations for 81xx to support dm814x
ARM: OMAP2+: Add minimal clockdomains for dm814x
ARM: OMAP2+: Fix scm compatible for dm814x
ARM: OMAP2+: Fix dm814x DT_MACHINE_START
ARM: OMAP2+: Remove module references from IOMMU machine layer
ARM: DRA7: Provide proper IO map table
ARM: OMAP2+: Clean up omap4_local_timer_init
ARM: OMAP2: Delete an unnecessary check
ARM: OMAP2+: sparse: add missing function declarations
ARM: OMAP2+: sparse: add missing static declaration
ARM: OMAP2+: hwmod: add support for lock and unlock hooks
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Renesas ARM Based SoC Updates for v4.3
* Add basic support for gose/r8a7793
* tag 'renesas-soc-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: gose: enable R-Car Gen2 regulator quirk
ARM: shmobile: Basic r8a7793 SoC support
Signed-off-by: Olof Johansson <olof@lixom.net>
Second Round of Renesas ARM Based SoC DT Updates for v4.3
* Add Audio MIX and CTU support to r8a779[01] SoCs
* Correct IRQ sense for adv7511 on lager board
* Add sound label to koelsch and lager boards
* Add IIC support to emev2 SoC
* tag 'renesas-dt2-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7791: Add Audio MIX support on DTSI
ARM: shmobile: r8a7791: Add Audio CTU support on DTSI
ARM: shmobile: r8a7790: Add Audio MIX support on DTSI
ARM: shmobile: r8a7790: Add Audio CTU support on DTSI
ARM: shmobile: lager: Fix adv7511 IRQ sensing
ARM: shmobile: koelsch: add sound label on DTS
ARM: shmobile: lager: add sound label on DTS
ARM: shmobile: emev2: kzm9d: enable IIC busses
ARM: shmobile: emev2: add IIC cores to dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>
Second Round of Renesas ARM Based SoC Cleanup for v4.3
* Silence APMU build warnings
* tag 'renesas-cleanup2-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: apmu: silence build warnings
Signed-off-by: Olof Johansson <olof@lixom.net>
STM32 DT updates for v4.3, round 1.
Highlights:
-----------
- Add RCC clocks support to STM32F429
- Add STM32429i-EVAL board support
- Use stdout-path instead of linux,stdout-path in Disco board
* tag 'stm32-dt-for-v4.3-1b' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/stm32:
ARM: dts: Use stdout-path in STM32F429 Discovery board
ARM: dts: Add STM32429i-EVAL board support
ARM: dts: stm32f429: Adopt STM32F4 clock driver
Signed-off-by: Olof Johansson <olof@lixom.net>
STi SoC updates for v4.3, round 1.
Highlights:
-----------
- Add code to release secondary cores from holding pen.
- Remove useless call to trace_hardirqs_off() in secondary core init function.
* tag 'sti-soc-for-v4.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti:
ARM: STi: Remove platform call to trace_hardirqs_off()
ARM: STi: Add code to release secondary cores from holding pen.
Signed-off-by: Olof Johansson <olof@lixom.net>
STi defconfig for v4.3, round 1
Highlights:
-----------
- Enable support ST's PWM driver in multi_v7
- Enable support PWM regulator in multi_v7
* tag 'sti-defconfig-for-v4.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti:
ARM: multi_v7_defconfig: Enable support for PWM Regulators
ARM: multi_v7_defconfig: Enable ST's PWM driver
Signed-off-by: Olof Johansson <olof@lixom.net>
Replace the deprecated atomic_{set,clear}_mask() usage with the now
ubiquous atomic_{or,andnot}() functions.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Move the now generic definitions of atomic_{set,clear}_mask() into
linux/atomic.h to avoid endless and pointless repetition.
Also, provide an atomic_andnot() wrapper for those few archs that can
implement that.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
These will replace the atomic_{set,clear}_mask functions that are
available on some archs.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Implement atomic logic ops -- atomic_{or,xor,and}.
For tilegx, these are relatively straightforward; the architecture
provides atomic "or" and "and", both 32-bit and 64-bit. To support
xor we provide a loop using "cmpexch".
For the older 32-bit tilepro architecture, we have to extend
the set of low-level assembly routines to include 32-bit "and",
as well as all three 64-bit routines. Somewhat confusingly,
some 32-bit versions are already used by the bitops inlines, with
parameter types appropriate for bitops, so we have to do a bit of
casting to match "int" to "unsigned long".
Signed-off-by: Chris Metcalf <cmetcalf@ezchip.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1436474297-32187-1-git-send-email-cmetcalf@ezchip.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
