Commit Graph

5 Commits

Author SHA1 Message Date
Stephen Boyd
a7c602bf42 Merge tag 'tegra-for-4.3-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-next
clk: tegra: Changes for v4.3-rc1

This contains the DFLL driver needed to implement CPU frequency scaling
on Tegra.
2015-08-25 15:55:28 -07:00
Stephen Boyd
584ac4e935 clk: tegra: Properly include clk.h
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h include that was missing in a file
using clkdev APIs.

Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2015-07-20 11:11:17 -07:00
Tuomas Tynkkynen
79cf95c763 clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
The DFLL clocksource was missing from the list of possible parents for
the fast CPU cluster. Add it to the list.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-07-16 10:40:20 +02:00
Andrew Bresticker
88b4bd7071 clk: tegra: cclk_lp has a pllx/2 divider
When pll_x is the parent of cclk_lp, PLLX_DIV2_BYPASS_LP determines
whether cclk_lp output is divided by 2.  Set TEGRA_DIVIDER_2 so that
the clk_super driver is aware of this.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:28 +02:00
Peter De Schrijver
a7c8485a0e clk: tegra: introduce common gen4 super clock
Introduce a common function which performs super clock initialization for
Tegra114 and beyond.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2013-11-26 18:46:50 +02:00