Set connectors_changed to force a modeset if the panel fitter's force
enabled on eDP.
Changes since v1:
- Use connectors_changed instead of active_changed because it's a
routing update.
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Two small bug fixes for the code you pulled for 4.3:
- Used a SHIFT define instead of a MASK define to check if a bit is turned on
when destroying hqd. Luckily, this is in gfx7 interface file with amdgpu,
which was used only for bring-up purposes of amdgpu, so no real effect on
a running system
- Used a logical AND instead of a bitwise AND operator, when initializing
sdma virtual memory when using SDMA queues
* tag 'drm-amdkfd-next-fixes-2015-08-05' of git://people.freedesktop.org/~gabbayo/linux:
drm/amdkfd: fix bug when initializing sdma vm
drm/amdgpu: fix bug when amdkfd destroys hqd
This serie of patches fix minor bugs around how driver sub-components are
bind and planes z-ordering.
The main part is about atomic support: using more atomic helpers allow us
to simplify the code (~300 lines removed) and to ahve a better match between
drm concepts (planes and crtc) and hardware split.
[airlied: fixed up conflict in atomic code]
* 'drm-sti-next-atomic-2015-08-11' of http://git.linaro.org/people/benjamin.gaignard/kernel:
drm/sti: atomic crtc/plane update
drm/sti: rename files and functions
drm/sti: code clean up
drm/sti: fix dynamic z-ordering
drm: sti: fix sub-components bind
This reverts commit 1addc12648
This commit seems to cause crashes in gk104_fifo_intr_runlist() by
returning 0xbad0da00 when register 0x2a00 is read. Since this commit was
intended for GM20B which is not completely supported yet, let's revert
it for the time being.
Reported-by: Eric Biggers <ebiggers3@gmail.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Tested-by: Afzal Mohammed <afzal.mohd.ma@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This addresses two issues that cause problems with viewperf maya-03 in
situation with memory pressure.
The first issue causes attempts to unreserve buffers if batched
reservation fails due to, for example, a signal pending. While previously
the ttm_eu api was resistant against this type of error, it is no longer
and the lockdep code will complain about attempting to unreserve buffers
that are not reserved. The issue is resolved by avoid calling
ttm_eu_backoff_reservation in the buffer reserve error path.
The second issue is that the binding_mutex may be held when user-space
fence objects are created and hence during memory reclaims. This may cause
recursive attempts to grab the binding mutex. The issue is resolved by not
holding the binding mutex across fence creation and submission.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
The likelihood of getting a large number of panel drivers from different
vendors is quite high. Add a prefix to the two existing Samsung panel
drivers to set a guideline for future patch submissions. Using vendor
prefixes consistently should allow a cleaner organization of the tree.
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Now that the PTN3460 driver has been rewritten as a proper I2C driver
and there is infrastructure to hook up the bridge with a DRM device, it
is no longer necessary to have this dependency to ensure the correct
build mode.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The SOR1 introduced on Tegra210 supports HDMI 2.0 and DisplayPort. Add
HDMI support and name the debugfs node after the type of SOR. The SOR
introduced with Tegra124 is known simply as "sor", whereas the
additional SOR found on Tegra210 is known as "sor1".
Signed-off-by: Thierry Reding <treding@nvidia.com>
The SOR found on Tegra210 is very similar to the version found on
Tegra124, except that it no longer supports LVDS.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Move all code into the new canonical ->disable() and ->enable() helper
callbacks so that they play extra nice with atomic DPMS.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order to restore DPMS with atomic mode-setting, move all code from
the ->mode_set() callback into ->enable(). At the same time, rename the
->prepare() callback to ->disable() to use the names preferred by atomic
mode-setting. This simplifies the calling sequence and will allow DPMS
to use runtime PM in subsequent patches.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order to restore DPMS with atomic mode-setting, move all code from
the ->mode_set() callback into ->enable(). At the same time, rename the
->prepare() callback to ->disable() to use the names preferred by atomic
mode-setting. This simplifies the calling sequence and will allow DPMS
to use runtime PM in subsequent patches.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order to restore DPMS with atomic mode-setting, move all code from
the ->mode_set() callback into ->enable(). At the same time, rename the
->prepare() callback to ->disable() to use the names preferred by atomic
mode-setting. This simplifies the calling sequence and will allow DPMS
code to use runtime PM in subsequent patches.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In order to restore DPMS with atomic mode-setting, move all code from
the ->mode_set() callback into ->enable(). At the same time, rename the
->prepare() callback to ->disable() to use the names preferred by atomic
mode-setting. This simplifies the calling sequence and will allow DPMS
code to use runtime PM in subsequent patches.
While at it, remove the enabled field that hasn't been used since the
demidlayering of the output drivers done in preparation for the atomic
mode-setting conversion.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Instead of duplicating most of the code to set up a debugfs file, use
the existing DRM core debugfs infrastructure instead.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The head state registers are per head, so they must be properly indexed.
This has worked fine so far because all boards with eDP use it as the
primary output, so it is very likely to end up attached to head 0.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The data structure is always only read, never written, and can hence be
referred to by a const pointer.
Signed-off-by: Thierry Reding <treding@nvidia.com>
When tearing down debugfs support, make sure to reset the fields to NULL
in the correct order, otherwise the debugfs root will not be properly
removed.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DRM minor is needed to teardown debugfs, so it needs to be tracked
to prevent a crash on driver removal.
Signed-off-by: Thierry Reding <treding@nvidia.com>
When probing the SOR device fails, output proper error messages to help
diagnose the cause of the failure.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The TRM lists indexed registers without an underscore to separate name
from index. Use that convention in the driver for consistency.
While at it, rename some of the field names to the names used in the
TRM.
Signed-off-by: Thierry Reding <treding@nvidia.com>
When the DPAUX isn't attached to an SOR the interrupts are not useful.
This also prevents a race that could potentially cause a crash on driver
removal.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DPAUX code paths already configure the pads in AUX mode, but there
is no way to reconfigure them in I2C mode for HDMI (the DPAUX module is
unused in that case). Enabling the pads in I2C mode by default is the
quickest way to support HDMI. Eventually this may need an explicit call
in the user drivers.
Signed-off-by: Thierry Reding <treding@nvidia.com>
When probing the dpaux device fails, output proper error messages to
help diagnose the cause of the failure.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DSI host controller hasn't changed from Tegra132 to Tegra210, but
different characterization parameters may be required.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DSI host controller hasn't changed from Tegra124 to Tegra132, but
different characterization parameters may be required.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The DSI host controller hasn't changed from Tegra114 to Tegra124, but
different characterization parameters may be required.
Signed-off-by: Thierry Reding <treding@nvidia.com>
In video modes without sync pulses, the horizontal back-porch needs to
include the horizontal sync width.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The call to platform_driver_register() will already set up the .owner
field, so there's no need to do it explicitly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The horizontal pulse enable bits are named H_PULSE{0,1,2}_ENABLE in the
TRM. Modify the driver to use the same naming for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Record interrupt statistics, such as the number of frames and VBLANKs
received and the number of FIFO underflow and overflows.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Request a syncpoint for display prior to registering the host1x client.
This will ensure that the syncpoint will be acquired when the KMS driver
initializes.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Upon driver load, reset the VBLANK machinery to off to reflect the
hardware state. Since the ->reset() callback is called from the initial
drm_mode_config_reset() call, move the latter after the VBLANK machinery
initialization by drm_vblank_init().
Signed-off-by: Thierry Reding <treding@nvidia.com>
Keep track of the number of users of DSI and CSI pads and power down the
regulators that supply the bricks when all users are gone.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Some changes are needed to the configuration settings for some lanes. In
addition, the clock lanes for the CSI pads can no longer be calibrated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
While Tegra132 has the same pads as Tegra124, some configuration values
need to be programmed slightly differently.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Before starting a new calibration cycle, make sure to clear the current
status by writing a 1 to the various "calibration done" bits.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Parameterize more of the register programming to accomodate for changes
required by future SoC generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
