Krzysztof Kozlowski
3b83eea633
dt-bindings: PCI: qcom,pcie-x1e80100: Add missing required power-domains and resets
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Power domains and resets should be required for PCI, so the proper SoC
supplies are turned on.
Fixes: 692eadd516krzysztof.kozlowski@linaro.org >
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org >
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Link: https://patch.msgid.link/20251030-dt-bindings-pci-qcom-fixes-power-domains-v2-9-28c1f11599fe@linaro.org
2025-11-17 18:33:23 +05:30
Manivannan Sadhasivam
e3d7fda088
dt-bindings: PCI: Update the email address for Manivannan Sadhasivam
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My linaro email id is no longer active. So switch to kernel.org one.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com >
Link: https://patch.msgid.link/20251010-pci-binding-v1-1-947c004b5699@oss.qualcomm.com
Acked-by: Rob Herring (Arm) <robh@kernel.org >
2025-10-26 21:26:34 +05:30
Qiang Yu
96a17ed17b
dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller
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On the Qualcomm Glymur platform, the fifth PCIe host is compatible with
the DWC controller present on the X1E80100 platform, but does not have
cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com >
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com >
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com >
Acked-by: Rob Herring (Arm) <robh@kernel.org >
Link: https://patch.msgid.link/20250919142325.1090059-1-pankaj.patil@oss.qualcomm.com
2025-09-26 16:14:21 -05:00
Qiang Yu
66dc205962
dt-bindings: PCI: qcom,pcie-x1e80100: Add 'global' interrupt
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Qcom PCIe RC controllers are capable of generating 'global' SPI interrupt
to the host CPU. This interrupt can be used by the device driver to handle
PCIe link specific events such as Link up and Link down, which give the
driver a chance to start bus enumeration on its own when link is up and
initiate link training if link goes to a bad state. The PCIe driver can
still work without this interrupt but it will provide a nice user
experience when device gets plugged and removed.
Hence, document it in the binding along with the existing MSI interrupts.
Global interrupt is parsed as optional in driver, so adding it in bindings
will not break the ABI.
Link: https://lore.kernel.org/r/20241101030902.579789-3-quic_qianyu@quicinc.com
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com >
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2024-11-03 20:12:41 +00:00
Abel Vesa
30e7c6cc88
dt-bindings: PCI: qcom: x1e80100: Make the MHI reg region mandatory
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All PCIe controllers found on X1E80100 have MHI register region.
So change the schema to reflect that.
Fixes: 692eadd516https://lore.kernel.org/linux-pci/20240605-x1e80100-pci-bindings-fix-v2-1-c465e87966fc@linaro.org
Signed-off-by: Abel Vesa <abel.vesa@linaro.org >
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org >
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2024-07-04 14:46:15 +00:00
Abel Vesa
692eadd516
dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller
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Add dedicated schema for the PCIe controllers found on X1E80100.
Link: https://lore.kernel.org/linux-pci/20240301-x1e80100-pci-v4-1-7ab7e281d647@linaro.org
Signed-off-by: Abel Vesa <abel.vesa@linaro.org >
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org >
2024-03-10 17:55:07 +00:00
