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31 Commits

Author SHA1 Message Date
Jani Nikula
4341dd24ab drm/i915/ltphy: include intel_display_utils.h instead of i915_utils.h 
Display code stopped using i915_utils.h in favour of
intel_display_utils.h. Fix recent additions.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20251112181342.107911-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
 2025-11-13 10:27:10 +02:00
Ville Syrjälä
6be05d5b28 drm/i915/de: Use intel_de_wait_for_{set,clear}_ms() 
Use intel_de_wait_for_{set,clear}_ms() instead of
intel_de_wait_ms() where appropriate.

Done with cocci (with manual formatting fixes):
@@
identifier func !~ "intel_de_wait_for";
expression display, reg, mask, timeout_ms;
@@
func(...)
{
<...
(
- intel_de_wait_ms(display, reg, mask, mask, timeout_ms, NULL)
+ intel_de_wait_for_set_ms(display, reg, mask, timeout_ms)
|
- intel_de_wait_ms(display, reg, mask, 0, timeout_ms, NULL)
+ intel_de_wait_for_clear_ms(display, reg, mask, timeout_ms)
)
...>
}

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251110172756.2132-11-ville.syrjala@linux.intel.com
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
 2025-11-11 19:31:44 +02:00
Ville Syrjälä
0aed9d3454 drm/i915/de: Use intel_de_wait_for_{set,clear}_us() 
Use intel_de_wait_for_{set,clear}_us() instead of
intel_de_wait_us() where appropriate.

Done with cocci (with manual formatting fixes):
@@
identifier func !~ "intel_de_wait_for";
expression display, reg, mask, timeout_us;
@@
func(...)
{
<...
(
- intel_de_wait_us(display, reg, mask, mask, timeout_us, NULL)
+ intel_de_wait_for_set_us(display, reg, mask, timeout_us)
|
- intel_de_wait_us(display, reg, mask, 0, timeout_us, NULL)
+ intel_de_wait_for_clear_us(display, reg, mask, timeout_us)
)
...>
}

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251110172756.2132-10-ville.syrjala@linux.intel.com
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
 2025-11-11 19:31:09 +02:00
Ville Syrjälä
8da977a2f2 drm/i915/de: Use intel_de_wait_ms() for the obvious cases 
Replace some users of intel_de_wait_custom() with intel_de_wait_ms().

This includes the cases where we pass in the default 2 microsecond
fast timeout, which is also what intel_de_wait_ms() uses so there
are no functional changes here.

Done with cocci (with manual formatting fixes):
@@
expression display, reg, mask, value, timeout_ms, out_value;
@@
- intel_de_wait_custom(display, reg, mask, value, 2, timeout_ms, out_value)
+ intel_de_wait_ms(display, reg, mask, value, timeout_ms, out_value)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251110172756.2132-7-ville.syrjala@linux.intel.com
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
 2025-11-11 19:29:24 +02:00
Ville Syrjälä
45554c1c64 drm/i915/de: Use intel_de_wait_us() 
Convert some of the intel_de_wait_custom() users over to
intel_de_wait_us(). We'll eventually want to eliminate
intel_de_wait_custom() as it's a hinderance towards using
poll_timeout_us().

This includes all the obvious cases where we only specify
a microsecond timeout to intel_de_wait_custom().

Done with cocci (with manual formatting fixes):
@@
expression display, reg, mask, value, timeout_us, out_value;
@@
- intel_de_wait_custom(display, reg, mask, value, timeout_us, 0, out_value)
+ intel_de_wait_us(display, reg, mask, value, timeout_us, out_value)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251110172756.2132-6-ville.syrjala@linux.intel.com
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
 2025-11-11 19:28:54 +02:00
Ville Syrjälä
93e0f7c8a9 drm/i915/de: Include units in intel_de_wait*() function names 
intel_de_wait*() take the timeout in milliseconds. Include
that information in the function name to make life less
confusing. I'll also be introducing microsecond variants
of these later.

Done with cocci:
@@
@@
(
static int
- intel_de_wait
+ intel_de_wait_ms
 (...)
{
...
}
|
static int
- intel_de_wait_fw
+ intel_de_wait_fw_ms
 (...)
{
...
}
|
static int
- intel_de_wait_for_set
+ intel_de_wait_for_set_ms
 (...)
{
...
}
|
static int
- intel_de_wait_for_clear
+ intel_de_wait_for_clear_ms
 (...)
{
...
}
)

@@
@@
(
- intel_de_wait
+ intel_de_wait_ms
|
- intel_de_wait_fw
+ intel_de_wait_fw_ms
|
- intel_de_wait_for_set
+ intel_de_wait_for_set_ms
|
- intel_de_wait_for_clear
+ intel_de_wait_for_clear_ms
)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251110172756.2132-4-ville.syrjala@linux.intel.com
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
 2025-11-11 19:27:46 +02:00
Suraj Kandpal
fa4aa0b271 drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithm 
Return the lowest port clock for HDMI when the reverse algorithm
calculates it to be 0 to avoid errors later but throw a warn.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251110061940.545183-2-suraj.kandpal@intel.com
 2025-11-10 15:58:10 +05:30
Suraj Kandpal
6fedb7bf73 drm/i915/ltphy: Implement HDMI Algo for Pll state 
Implement the HDMI Algorithm to dynamically create LT PHY state
based on the port clock provided.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251110061940.545183-1-suraj.kandpal@intel.com
 2025-11-10 15:55:26 +05:30
Ville Syrjälä
177deeea4d drm/i915/ltphy: Nuke bogus weird timeouts 
The LT PHY code is abusing intel_de_wait_custom() in all kinds of weird
ways. Get rid of the weird fast timeouts, and just use the slow ones.
For consistency with intel_wait_for_register() we'll stick to the
default 2 usec fast timeout for all cases.

Someone really needs to properly document where all these magic numbers
came from...

This will let us eventually nuke intel_de_wait_custom() and convert
over to poll_timeout_us().

v2: Go for the longer (ms) timeout in case it actually matters

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251106152049.21115-9-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2025-11-07 20:29:43 +02:00
Ville Syrjälä
2d41de2565 drm/i915/cx0: s/XELPDP_MSGBUS_TIMEOUT_SLOW/XELPDP_MSGBUS_TIMEOUT_MS/ 
The slow vs. fast timeout stuff is really just an implementation
detail. Let's not spread that terminology in random timeout defines.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251106152049.21115-7-ville.syrjala@linux.intel.com
 2025-11-07 20:29:43 +02:00
Ville Syrjälä
dfd58249ff drm/i915/ltphy: Nuke extraneous timeout debugs 
The actual timeout used isn't particularly interesting, so
don't print it. Makes the code simpler.

The debugs are also using some random capitalizaton rule.
Clean that up a bit while at it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251106152049.21115-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
 2025-11-07 20:29:43 +02:00
Suraj Kandpal
ad7108f966 drm/i915/ltphy: Modify the step that need to be skipped 
Bspec has changed the non tbt pll enable sequence now we skip
steps 5-17 if no config change has occurred.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-26-suraj.kandpal@intel.com
 2025-11-01 09:04:26 +05:30
Suraj Kandpal
9dcf183632 drm/i915/ltphy: Define LT PHY PLL state verify function 
Define function to verify the LT PHY PLL state function and call it
in intel_modeset_verify_crtc.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-24-suraj.kandpal@intel.com
 2025-11-01 09:04:22 +05:30
Suraj Kandpal
89e0a91e89 drm/i915/ltphy: Define function to readout LT Phy PLL state 
Define a function to readout hw state for LT Phy PLL which
can be used in get_config function call.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-23-suraj.kandpal@intel.com
 2025-11-01 09:04:20 +05:30
Suraj Kandpal
3a6f155ce0 drm/i915/ltphy: Define the LT Phy state compare function 
Define function to compare the state and if mismatch is detected
dump both the states.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-22-suraj.kandpal@intel.com
 2025-11-01 09:04:18 +05:30
Suraj Kandpal
a54bdcb714 drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence 
We need to enable and disable the Tx for each active lane after the
Non-TBT enable sequence is done.

Bspec: 74500, 74497, 74701
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-21-suraj.kandpal@intel.com
 2025-11-01 09:04:17 +05:30
Suraj Kandpal
13ba213f92 drm/i915/ltphy: Program LT Phy Voltage Swing 
Program LT Phy voltage swing using the Swing tables and plug in the
function at encoder->set_signal_level

Bspec: 74493
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-20-suraj.kandpal@intel.com
 2025-11-01 09:04:14 +05:30
Suraj Kandpal
109289252f drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences 
Hook up the LT Phy enable and disable sequences using encoder->
enable/disable_clock and reusing the TBT enable disable sequence from
cx0 PHY since it remains the same.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-18-suraj.kandpal@intel.com
 2025-11-01 09:04:10 +05:30
Suraj Kandpal
fa5fd596bf drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence 
Program in the steps for Non TBT PLL disable sequence.
The whole function can be defined in one shot since most of
prequiste functions are already coded in.

Bspec: 74492
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-17-suraj.kandpal@intel.com
 2025-11-01 09:04:08 +05:30
Suraj Kandpal
32865c2da5 drm/i915/ltphy: Program the rest of the LT Phy Enable sequence 
Program the rest of the LT Phy Non TBT PLL Enable sequence. This
can be done in a single patch since the rest of the prequistie
functions are already coded in.

Bspec: 74492, 69701
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-16-suraj.kandpal@intel.com
 2025-11-01 09:04:06 +05:30
Suraj Kandpal
82b4608323 drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps 
Program the rest of the steps with regards to PORT_CLOCK_CTL in
Non-TBT PLL enable sequence.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-15-suraj.kandpal@intel.com
 2025-11-01 09:04:05 +05:30
Suraj Kandpal
41d07bd25a drm/i915/ltphy: Program the P2P Transaction flow for LT Phy 
Program the LT PHY P2P transaction which uses P2M cycle to get
get data fro Phy when it is ready and then go read the MAC register
from the MAC address space.

Bspec: 68966, 74497, 74483, 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-14-suraj.kandpal@intel.com
 2025-11-01 09:04:02 +05:30
Suraj Kandpal
2435a11d72 drm/i915/ltphy: Add function to calculate LT PHY port clock 
Create a reverse algorithm which is used to find port clock
from the LT PHY state is provided which is used for
comparision & verification functions.

Bspec: 74667
Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-13-suraj.kandpal@intel.com
 2025-11-01 09:04:00 +05:30
Suraj Kandpal
3383ba2479 drm/i915/ltphy: Enable SSC during port clock programming 
We enable SSC when we program PORT_CLOCK_CTL register. We logically
determine if ssc is enabled or not while we calculate our state.

Bspec: 74492, 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-12-suraj.kandpal@intel.com
 2025-11-01 09:03:59 +05:30
Suraj Kandpal
4f1118bf96 drm/i915/ltphy: Update the ltpll config table value for eDP 
When we get the eDP tables we reuse dp tables for some data rates.
We need to modify the 3rd config value of this table to 1 instead
of 0 since that is the only difference in the dp and edp table for
that particular data rate.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-11-suraj.kandpal@intel.com
 2025-11-01 09:03:58 +05:30
Suraj Kandpal
1dd885d509 drm/i915/ltphy: Program the VDR PLL registers for LT PHY 
Fetch the tables which need to be used and program it in
the specified VDR register space. Everything is done over
the respective lanes.

Bspec: 68862, 74500
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-10-suraj.kandpal@intel.com
 2025-11-01 09:03:56 +05:30
Suraj Kandpal
dc5742b619 drm/i915/ltphy: Add LT Phy Programming recipe tables 
Add the LT Phy programming recipe tables for eDP, DP & HDMI and a
function to use the correct table.

Bspec: 74667
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-9-suraj.kandpal@intel.com
 2025-11-01 09:03:53 +05:30
Suraj Kandpal
e1455196ad drm/i915/ltphy: Read PHY_VDR_0_CONFIG register 
Read PHY_VDR_0_CONFIG to check if there is any change in the register and
decide based on that if P2P sequence to change the data rate of LT PHY
are required or not. This scenario only happens if the requested mode
uses 1.62Gbps with DP mode since LT PHY defaults to this mode if
any other mode is requested we need to follow the whole sequence.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-8-suraj.kandpal@intel.com
 2025-11-01 09:03:51 +05:30
Suraj Kandpal
fc9be0a10c drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence 
Add a wrapper on cx0 powerdown change sequence for LT Phy usage,
as the sequence remains unchanged when going from SNPS Phy to
LT Phy.

Bspec: 74495
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-7-suraj.kandpal@intel.com
 2025-11-01 09:03:49 +05:30
Suraj Kandpal
3a323c7e96 drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy 
Program sequence from port clock ctl except for the SSC
enablement part which will be taken care of later.

Bspec: 74492
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-6-suraj.kandpal@intel.com
 2025-11-01 09:03:47 +05:30
Suraj Kandpal
154ebdb77a drm/i915/ltphy: Phy lane reset for LT Phy 
Define function to bring phy lane out of reset for LT Phy and the
corresponding pre-requisite steps before we follow the steps for
Phy lane reset. Also create a skeleton of LT PHY PLL enable sequence
function in which we can place this function

Bspec: 77449, 74749, 74499, 74495, 68960
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-4-suraj.kandpal@intel.com
 2025-11-01 09:03:42 +05:30