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885 Commits

Author SHA1 Message Date
Rex Zhu
4d454e9ffd drm/amd/pp: Fix truncated clock value when set watermark 
the clk value should be tranferred to MHz first and
then transfer to uint16. otherwise, the clock value
will be truncated.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reported-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2018-11-13 10:20:41 -05:00
Evan Quan
108110a3ff drm/amd/powerplay: always use fast UCLK switching when UCLK DPM enabled 
With UCLK DPM enabled, slow switching is not supported any more.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-11-07 18:20:40 -05:00
Evan Quan
3c7eda0b65 drm/amd/powerplay: set a default fclk/gfxclk ratio 
Otherwise big gap between these two clocks may causes
some hangs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-11-07 18:20:32 -05:00
Rex Zhu
a4c3f247ee drm/amd/pp: Print warning if od_sclk/mclk out of range 
print warning in dmesg to notify user the setting for
sclk_od/mclk_od out of range that vbios can support

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-11-01 09:52:43 -05:00
Rex Zhu
47fdd89753 drm/amd/pp: Fix pp_sclk/mclk_od not work on Vega10 
not update dpm table with user's setting.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-11-01 09:52:33 -05:00
Rex Zhu
17c7c7e714 drm/amd/pp: Fix pp_sclk/mclk_od not work on smu7 
not update the dpm table with user's setting

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-11-01 09:52:24 -05:00
Evan Quan
1ecd0da588 drm/amd/powerplay: revise Vega20 pptable version check 
Tell the version numbers when the pptable versions do not match.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-30 16:53:28 -05:00
Evan Quan
3732eb0683 drm/amd/powerplay: commonize the API for retrieving current clocks 
So that it can be shared between all clocks.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu<Feifei.Xu@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-25 14:04:03 -05:00
Evan Quan
7dc94969e1 drm/amd/powerplay: correct the clocks for DAL to be Khz unit 
Currently the clocks reported are in 10Khz unit. Correct them
as Khz unit as DAL wanted.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu<Feifei.Xu@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-25 14:03:35 -05:00
Evan Quan
355c8db13b drm/amd/powerplay: commit get_performance_level API as DAL needed 
This can suppress the error reported on driver loading. Also these
are empty APIs as Vega12/Vega20 has no performance levels.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-24 20:03:24 -05:00
Evan Quan
3b2ad16dc4 drm/amd/powerplay: bump the PPtable version supported 
As the matching VBIOS is already ready. Also drop the
temporary workarounds applied before.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-22 14:43:02 -05:00
Evan Quan
b44ec6a3eb drm/amd/powerplay: drop highest UCLK setting after display configuration change 
The UCLK is forced to highest at the start of display configuration
change. Downgrade the UCLK from highest after display configuration change.
Otherwise, we may see the UCLK stuck in the highest in some cases.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-22 14:42:46 -05:00
David Francis
f191415b24 powerplay: Respect units on max dcfclk watermark 
In a refactor, the watermark clock inputs to
powerplay from DC were changed from units of 10kHz to
kHz clocks.

One division by 100 was not converted into a division
by 1000.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-22 14:41:05 -05:00
Evan Quan
e26f70a653 drm/amd/powerplay: update PPtable with DC BTC and Tvr SocLimit fields 
Update the PPtable structure to fit the latest SMC firmware.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-16 15:09:10 -05:00
Evan Quan
d579fd8270 drm/amd/powerplay: added I2C controller configuration 
PPTABLE structure is stretched to add I2C controller
configuration. Hold on the PPTABLE_V20_SMU_VERSION bump
until the VBIOS is ready.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-16 15:08:54 -05:00
Evan Quan
73d0a44669 drm/amd/powerplay: translate power_profile mode to pplib workload type 
Correctly translate the power profile specified by user to workload
type accepted by SMU fw.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-12 12:22:16 -05:00
Alex Deucher
a553c19d15 drm/amdgpu/powerplay: factor out some pptable helpers 
Move copy_array helpers to smu_helper.c and share between
vega12 and vega20.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-10 14:49:44 -05:00
Alex Deucher
99e219521d drm/amdgpu/powerplay: endian fixes for vega20_processpptables.c 
Properly swap data from vbios.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-10 14:49:44 -05:00
Alex Deucher
d97a7ab394 drm/amdgpu/powerplay: endian fixes for vega12_processpptables.c 
Properly swap data from vbios.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-10 14:49:43 -05:00
Alex Deucher
de50176330 drm/amdgpu/powerplay: endian fixes for vega10_processpptables.c 
Properly swap data from vbios.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-10 14:49:43 -05:00
Rex Zhu
7a3e0bb2a5 drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2 
Extract the function of fw loading out of powerplay.
Do fw loading between hw_init/resuem_phase1 and phase2

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-10 14:49:21 -05:00
Rex Zhu
5e161e5442 drm/amd/pp: Refine smu7/8 request_smu_load_fw callback function 
The request_smu_load_fw of VI is used to load gfx/sdma
ip's firmware.

Check whether the gfx/sdma firmware have been loaded successfully
in this callback function.
if failed, driver can exit to avoid gpu hard hung.
if successful, clean the flag reload_fw to avoid duplicated fw load.
when suspend/resume, driver need to reload fw.
so in suspend, reset the reload_fw flag to true to enable load fw when
resume.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 17:05:53 -05:00
Rex Zhu
d5f480372c drm/amd/pp: Implement AMDGPU_PP_SENSOR_MIN/MAX_FAN_RPM 
so user can query the RPM range

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 17:04:52 -05:00
Akshu Agrawal
51ef434a15 drm/amd/powerplay: Enable/Disable NBPSTATE on On/OFF of UVD 
We observe black lines (underflow) on display when playing a
4K video with UVD. On Disabling Low memory P state this issue is
not seen.
Multiple runs of power measurement shows no imapct.

Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2018-10-09 17:01:03 -05:00
Rex Zhu
d09ae92de8 drm/amdgpu: Move out power up/down sdma out of smu 
smu only expose interface to other ip blocks.
in order to reduce dependence between smu and other ip blocks

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 17:00:38 -05:00
Rex Zhu
40bea02f4a drm/amd/pp: Expose the smu support for SDMA PG cntl 
SDMA IP can be power up/down via smu message

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 17:00:32 -05:00
Rex Zhu
c52dcf4919 drm/amd/pp: Avoid divide-by-zero in fan_ctrl_set_fan_speed_rpm 
The minRPM speed maybe equal to zero. so need to check
input RPM not equal to 0, otherwise cause divide-by-zero driver crash.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 17:00:25 -05:00
Rex Zhu
b3ca0f397e drm/amd/pp: Fix fan's RPM setting not work on VI/Vega10 
set the target rpm value to wrong register.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 17:00:18 -05:00
Evan Quan
8010f2886a drm/amd/powerplay: enable MGPU fan boost feature on Vega20 
Added Vega20 specific implementation for MGPU fan boost
feature.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 17:00:05 -05:00
Alex Deucher
e92b83e508 drm/amdgpu/vega20: make power profile output more consistent 
Make the profile name line match previous generations more closely.

E.g.,
0 3D_FULL_SCREEN :
vs:
0(3D_FULL_SCREEN )

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 16:45:59 -05:00
Evan Quan
031db09017 drm/amd/powerplay/vega20: enable fan RPM and pwm settings V2 
Manual fan RPM and pwm setting on vega20 are
available now.

V2: correct the register for fan speed setting and
    avoid divide-by-zero

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 16:45:58 -05:00
Evan Quan
42fae99520 drm/amd/powerplay/vega20: tell the correct gfx voltage V2 
Export the correct gfx voltage by hwmon interface.

V2: update the register naming for consistency

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 16:45:58 -05:00
Evan Quan
3546916f42 drm/amd/powerplay/vega20: correct the hwmon interface ppt limit output 
The ppt limit read out by hwmon interface is always 0.
Correct this hwmon interface output.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-10-09 16:45:57 -05:00
Nathan Chancellor
3ea81f7125 drm/amd/powerplay: Change id parameter type in pp_atomfwctrl_get_clk_information_by_clkid 
Clang generates warnings when one enumerated type is implicitly
converted to another.

drivers/gpu/drm/amd/amdgpu/../powerplay/hwmgr/ppatomfwctrl.c:532:57:
warning: implicit conversion from enumeration type 'enum
atom_smu11_syspll0_clock_id' to different enumeration type 'BIOS_CLKID'
      (aka 'enum atom_smu9_syspll0_clock_id') [-Wenum-conversion]
        if (!pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
SMU11_SYSPLL0_SOCCLK_ID, &frequency))

In this case, that is expected behavior. To make that clear to Clang
without explicitly casting these values, change id's type to uint8_t
in pp_atomfwctrl_get_clk_information_by_clkid so no conversion happens.

Reported-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-27 09:40:09 -05:00
Christian König
1ffdeca648 drm/amdgpu: move more defines into amdgpu_irq.h 
Everything that isn't related to the IH ring.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:22 -05:00
Rex Zhu
d355f149d0 drm/amd/pp: Disable dpm features on smu7/8 when suspend 
Need to disable dpm features before halt rlc.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:19 -05:00
Alex Deucher
39a8a0db83 drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega20 
So we can query what features are enabled for debugging.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:11 -05:00
Alex Deucher
d152d373a6 drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega12 
So we can query what features are enabled for debugging.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:11 -05:00
Alex Deucher
1f6c52ed09 drm/amdgpu: implement ENABLED_SMC_FEATURES_MASK sensor for vega10 
So we can query what features are enabled for debugging.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:10 -05:00
Alex Deucher
a476e925ba drm/amdgpu/powerplay: add smu smc_table_manager callback for vega20 
For consistency with other asics.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:10 -05:00
Alex Deucher
68e841abf8 drm/amdgpu/powerplay: add smu smc_table_manager callback for vega12 
For consistency with other asics.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:09 -05:00
Alex Deucher
0b2c0a12cb drm/amdgpu/powerplay: Move vega10_enable_smc_features 
to vega10_smumgr.c.  For consistency with other vega parts.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:09 -05:00
Alex Deucher
d498a6e112 drm/amdgpu/powerplay: add get_argument callback for vega20 
For consistency with other vega parts.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:08 -05:00
Rex Zhu
0fb5da0a9b drm/amd/pp: Honour DC's clock limits on Rv 
Honour display's request for min engine clock/memory clock.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-26 21:09:04 -05:00
Evan Quan
32f2a0d117 drm/amd/powerplay: retrieve the updated clock table after OD 
With OD settings applied, the clock table will be updated accordingly.
We need to retrieve the new clock tables then.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-19 12:38:02 -05:00
Evan Quan
b1f82cb212 drm/amd/powerplay: update OD to take voltage value instead of offset 
With the latest SMC fw, we are able to get the voltage value for
specific frequency point. So, we update the OD relates to take
absolute voltage instead of offset.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-19 12:37:55 -05:00
Evan Quan
8a1304a5b4 drm/amd/powerplay: update OD feature judgement 
Update the conditions to judge whether an OD feature
should be supported on vega20.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-19 12:37:48 -05:00
Alex Deucher
741deade2a drm/amdgpu: simplify Raven, Raven2, and Picasso handling 
Treat them all as Raven rather than adding a new picasso
asic type.  This simplifies a lot of code and also handles the
case of rv2 chips with the 0x15d8 pci id.  It also fixes dmcu
fw handling for picasso.

Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-14 09:38:03 -05:00
Evan Quan
89da2a505f drm/amd/powerplay: disable raven2 force dpm level support (v2) 
It's not supported yet.

v2: rebase (Alex)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-14 09:37:09 -05:00
Evan Quan
fa27203f8a drm/amd/powerplay: round up the Mhz convertion (v2) 
Since the clock value there may be like 29999 10Khz.

v2: rebase (Alex)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-09-14 09:37:06 -05:00