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3 Commits

Author SHA1 Message Date
Gerhard Engleder
60e1b494ef dt-bindings: net: tsnep: Allow additional interrupts 
Additional TX/RX queue pairs require dedicated interrupts. Extend
binding with additional interrupts.

Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
 2022-09-30 11:31:34 +01:00
Gerhard Engleder
ff46c610ab dt-bindings: net: tsnep: Allow dma-coherent 
Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache
coherent.

Add "dma-coherent" property to allow the configuration of cache coherent
DMA.

Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
 2022-09-30 11:31:34 +01:00
Gerhard Engleder
603094b2cd dt-bindings: net: Add tsnep Ethernet controller 
The TSN endpoint Ethernet MAC is a FPGA based network device for
real-time communication.

It is integrated as normal Ethernet controller with
ethernet-controller.yaml and mdio.yaml.

Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
 2021-11-22 13:19:04 +00:00