Suggest by Arnd: abstract mmc tuning as clock behavior,
also because different soc have different tuning method and registers.
hi3620_mmc_clks is added to handle mmc clock specifically on hi3620.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
While we are here, also brush up the devicetree binding documentation.
The example was an inappropriate copy from the sh_mobile driver.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Add support for the led-mode property for the following PHYs
which have a single LED mode configuration value.
KSZ8001 and KSZ8041 which both use register 0x1e bits 15,14 and
KSZ8021, KSZ8031 and KSZ8051 which use register 0x1f bits 5,4
to control the LED configuration.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
Dove pinctrl binding now requires three different reg properties. This
updates corresponding binding and example accordingly. While at it, also
document reg property as required for the other MVEBU SoC pinctrl nodes.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Marvell Dove SoC binding was not documented, yet. Add the documentation
and also describe Global Configuration register node in it.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Marvell Armada 380/385 are new ARM SoCs from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
The Marvell Armada 375 is a new ARM SoC from Marvell, part of the
mvebu family, but using a Cortex-A9 CPU core. In terms of pin-muxing,
it is similar to Armada 370 and XP for the register layout, only
different in the number of available pins and their
functions. Therefore, we simply use the existing
drivers/pinctrl/mvebu/ infrastructure, with no other changes that the
list of pins and corresponding functions.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Merge "mvebu new SoCs for v3.15" from Jason Cooper:
- mvebu
- initial support for Armada 375, 380, and 385
Depends:
- tags/mvebu-soc-3.15 (resolves delete/rename hidden conflict)
* tag 'mvebu-soc-3xx-3.15' of git://git.infradead.org/linux-mvebu:
Documentation: arm: update Marvell documentation about Armada 375/38x
ARM: mvebu: add initial support for the Armada 380/385 SOCs
ARM: mvebu: add workaround for data abort issue on Armada 375
ARM: mvebu: add initial support for the Armada 375 SOCs
ARM: mvebu: add Armada 375 support to the system-controller driver
ARM: mvebu: make CPU_PJ4B selection a per-SoC choice
ARM: mvebu: rename DT machine structure for Armada 370/XP
ARM: mvebu: rename armada-370-xp.c to board-v7.c
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
mvebu watchdog driver changes for v3.15
- orion watchdog
- cleanup and extend driver to support Armada 370 and Armada XP
Depends:
- tags/irqchip-mvebu-fixes-3.14 (already pulled by tglx)
- both are based on v3.14-rc1
* tag 'mvebu-watchdog-3.15' of git://git.infradead.org/linux-mvebu:
watchdog: orion: Enable the build on ARCH_MVEBU
watchdog: orion: Add support for Armada 370 and Armada XP SoC
watchdog: orion: Add per-compatible watchdog start implementation
watchdog: orion: Add per-compatible clock initialization
watchdog: orion: Introduce per-compatible of_device_id data
watchdog: orion: Introduce an orion_watchdog device structure
watchdog: orion: Remove unneeded BRIDGE_CAUSE clear
watchdog: orion: Make RSTOUT register a separate resource
watchdog: orion: Handle the interrupt so it's properly acked
watchdog: orion: Make sure the watchdog is initially stopped
watchdog: orion: Remove unused macros
watchdog: orion: Use atomic access for shared registers
watchdog: orion: Add clock error handling
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The compatible string of the Broadcom Capri pinctrl driver is renamed to
"brcm,bcm11351-pinctrl" to match the machine binding here:
Documentation/devicetree/bindings/arm/bcm/bcm11351.txt
Signed-off-by: Sherman Yin <syin@broadcom.com>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
This patch adds descriptions for new properties of the device tree
binding for the ARM SMMU architecture. These properties control
arm-smmu driver options.
Cc: Grant Likely <grant.likely@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com>
[will: removed device isolation property, as this has been dropped and
fixed up spacing in documentation]
Signed-off-by: Will Deacon <will.deacon@arm.com>
The DT bindings document a renesas,indices property, while the code, the
DT example and the DT sources all use renesas,clock-indices. Fix the
documentation.
The shmobile mstp DT bindings have been merged in v3.14-rc1 with a bug
in the DT ABI, a fix during the -rc series is appropriate.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Simon Horman <horms@verge.net.au>
This cleanup series gets rid of <mach/timex.h> for platforms not using
ARCH_MULTIPLATFORM. (For multi-platform code it's already unused since
387798b (ARM: initial multiplatform support).)
To make this work some code out of arch/arm needed to be adapted. The
respective changes got acks by their maintainers to be taken via armsoc
(with Andrew Morton substituting for Alessandro Zummo as rtc maintainer).
Compared to the previous pull request there was another patch added that
fixes a (non-critical) regression on ixp4xx. Olof Johansson asked to not
squash this fix into the original commit to save him from the need to
reverify the series.
Conflicts:
arch/arm/mach-at91/at91sam9260.c
arch/arm/mach-at91/at91sam9261.c
arch/arm/mach-at91/at91sam9263.c
arch/arm/mach-at91/at91sam9rl.c
arch/arm/mach-mmp/time.c
arch/arm/mach-sa1100/time.c
Pull ARM SoC fixes from Olof Johansson:
"A collection of fixes for ARM platforms. Most are fixes for DTS
files, mostly from DT conversion on OMAP which is still finding a few
issues here and there.
There's a couple of small stale code removal patches that we usually
queue for the next release instead, but they seemed harmless enough to
bring in now.
Also, a fix for backlight on some PXA platforms, and a cache
configuration fix for Tegra, etc"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits)
MAINTAINERS: add additional ARM BCM281xx/BCM11xxx maintainer
ARM: tegra: only run PL310 init on systems with one
ARM: tegra: Add head numbers to display controllers
ARM: imx6: build pm-imx6q.c independently of CONFIG_PM
ARM: tegra: fix RTC0 alias for Cardhu
ARM: dove: dt: revert PMU interrupt controller node
Documentation: dt: OMAP: Update Overo/Tobi
ARM: dts: Add support for both OMAP35xx and OMAP36xx Overo/Tobi
ARM: dts: omap3-tobi: Use the correct vendor prefix
ARM: dts: omap3-tobi: Fix boot with OMAP36xx-based Overo
ARM: OMAP2+: Remove legacy macros for zoom platforms
ARM: OMAP2+: Remove MACH_NOKIA_N800
ARM: dts: N900: add missing compatible property
ARM: dts: N9/N950: fix boot hang with 3.14-rc1
ARM: OMAP1: nokia770: enable tahvo-usb
ARM: OMAP2+: gpmc: fix: DT ONENAND child nodes not probed when MTD_ONENAND is built as module
ARM: OMAP2+: gpmc: fix: DT NAND child nodes not probed when MTD_NAND is built as module
ARM: dts: omap3-gta04: Fix mmc1 properties.
ARM: dts: omap3-gta04: Fix 'aux' gpio key flags.
ARM: OMAP2+: add missing ARCH_HAS_OPP
...
clock: mvebu new SoC changes for v3.15
- mvebu (Armada 375/380/385)
- extend corediv clock driver to support new SoCs
- add core and gating clock drivers for new SoCs
Add a property called clock-indices to allow clock-output-names
to be used where the index used to lookup a clock is not a 1:1
mapping to the array position in the clock-output-names
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Jonathan writes:
Second round of IIO new driver, functionality and cleanups for the 3.15 series.
There are a few fixes in here that might, earlier in a cycle, have gone
to Greg as fixes. Given they are either minor or have never actually
been observed as causing trouble (the locking bug in the event code) and
are invasive, I have included them in this pull request, targeting the
3.15 merge window instead.
The rest are pretty uncontroversial new drivers, a handy little tool for
the example code in our documentation and little cleanups.
New drivers
* Freescale Vybrid and i.MX6SLX ADC driver.
* HID Sensor hub proximity sensors.
* HID Sensor hub pressure sensors.
* LPS25H Pressure sensors added to the ST micro pressure sensor driver.
New functionality
* lsiio tool. This is added to the staging tree as we haven't yet moved
the example code it sits with out. Moving this code out is now a reasonably
high priority but holding up this tool in the meantime did not seem
worthwhile.
* mag3110 - add missing scale factor for temperature output to userspace.
Cleanups
* Fix a bug in the event reporting in which a spin lock might be held over
when a sleep occured. A similar bug was found by Lars in the buffer code.
It has not to our knowledge been observed as actually occuring and is
a little too invasive to push out as a fix.
* Drop the IIO_ST macro after clearing out all users. This macro was a very
bad idea leading to a number of bugs after it stopped covering all elements
of the structure being assigned and people started making assumptions about
what it did cover. Glad to see it go!
* Avoid applying extended name to shared attributes as it makes no sense.
No in tree drivers were using the combination, hence not pushed out as
a fix.
* ad799x - move to devm_request_threaded_irq to reduce boilerplate clean up.
* bma180 - make the low_pass_filter_3db_frequency info element shared rather
than per attribute. The old approach was valid but not as clean as it might
be and was setting a bad example. Hence the cleanup.
* mxs-lradc - propogate the error code form a platform_get_irq call rather than
eating it up by returning -EINVAL on all errors.
* ad799x - typo fix in the copyright message. Either that or Michael was
asserting a copyright that moved backwards in time by about a thousand years.
* ad799x - use a regulator for vref rather than platform data. The driver
dates from just as the regulator framework was coming into common use so
provides an alternative way of specifying the reference voltage. We no
longer need that approach so drop it in favour of a regulator only approach.
* max1363 - some internal vref values were out by a small amount. The effect
would have been tiny and no one noticed hence not pushing this through as
a fix.
* core - replace some pointless goto error_ret (with no clean up) lines with
direct returns. This is my bad coding style so I'm glad to see it cleaned
up.
* core - avoid a kasprintf that just directly prints a string with no
formatting elements. This has always been there but Lars just noticed it.
Oops.
For some CPU/CODEC DAI devices the slot information maybe needed. This
patch adds the slot information parsing for simple-card driver.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Support regulators to power up the codec. This patch also enables the
AVDD LDO if no AV regulator was found.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
Add support for a master clock passed through DT. The master clock of
the codec is only active when the codec is in use.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
List full example compatible properties with soctypes instead of just the
soctypes, so checkpatch can validate DTSes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
The older Allwinner SoCs (A10, A13, A10s and A20) all have the same SPI
controller.
Unfortunately, this SPI controller, even though quite similar, is significantly
different from the recently supported A31 SPI controller (different registers
offset, split/merged registers, etc.). Supporting both controllers in a single
driver would be unreasonable, hence the addition of a new driver.
Like its more recent counterpart, it supports DMA, but the driver only does PIO
until we have a dmaengine driver for this platform.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Instantiate the L2 cache from DT. Indicate in DT where the cache
control register is so that it is possible to enable/disable write
through on the CPU.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The ahci_platform driver supports "snps,dwc-ahci".
Add this to the DT binding information.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
This avoids the ugliness of creating a nested platform device from probe.
While moving it around anyways, move the mk6q phy init code from probe
to imx_sata_enable, as the phy needs to be re-initialized on resume too,
otherwise the drive won't be recognized after resume.
Tested on a wandboard i.mx6 quad.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
This patch adds support for the ahci sata controler found on Allwinner A10
and A20 SoCs to the ahci_platform driver.
Orignally written by Olliver Schinagl using the approach of having a platform
device which probe method creates a new child platform device which gets
driven by ahci_platform.c, as done by ahci_imx.c .
Refactored by Hans de Goede to add most of the non sunxi specific functionality
to ahci_platform.c and use a platform_data pointer from of_device_id for the
sunxi specific bits.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
The allwinner-sun4i AHCI controller needs 2 clocks to be enabled and the
imx AHCI controller needs 3 clocks to be enabled.
tj: Minor comment formatting updates.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Provide the option to configure these speed modes per host, for those
host driver's that can't distinguish this in runtime.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Chris Ball <chris@printf.net>
Provide the option to configure these speed modes per host, for those
host driver's that can't distinguish this in runtime.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Chris Ball <chris@printf.net>
Provide the option to configure these speed modes per host, for those
host driver's that can't distinguish this in runtime.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Chris Ball <chris@printf.net>
The new Armada 375 and Armada 38x Marvell SoCs are based on Cortex-A9
CPU cores and use the ARM GIC as their main interrupt controller.
However, for various purposes (wake-up from suspend, MSI interrupts),
they have kept a separate MPIC interrupt controller, acting as a slave
to the GIC. This MPIC was already used as the primary controller on
previous Marvell SoCs, so this commit extends the existing driver to
allow the MPIC to be used as a GIC slave.
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Using the added infrastructure for handling SoC differences,
this commit adds support for the watchdog controller available
in Armada 370 and Armada XP SoCs.
Also, and because the AXP clock initialization uses of_clk_get_by_name,
this commit changes the orion clock initialization to use clk_get() and
adds a proper clk_put() on the common exit/error paths.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
In order to support other SoC, it's required to distinguish
the 'control' timer register, from the 'rstout' register
that enables system reset on watchdog expiration.
To prevent a compatibility break, this commit adds a fallback
to a hardcoded RSTOUT address.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
DT-enabled plaforms, where the irqchip driver for the brigde interrupt
controller is available, can handle the watchdog IRQ properly. Therefore,
request the interrupt and add a dummy handler that merely calls panic().
This is done in order to have an initial 'ack' of the interruption,
which clears the watchdog state.
Furthermore, since some platforms don't have such IRQ, this commit
makes the interrupt specification optional.
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Acked-by: Wim Van Sebroeck <wim@iguana.be>
Tested-By: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
