Merge "Exynos MCPM support for v3.16" from Kukjin Kim:
- adding MCPM backend support for SMP secondary boot and core switching
on Samsung's Exynos5420.
Tested on exynos5420-smdk5420 and exynos5420 based chromebook (peach-pit)
using the "/dev/b.L_switcher" user interface. Secondary core boot-up has
also been tested on both the boards.
* tag 'exynos-mcpm' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Add MCPM call-back functions
ARM: dts: add CCI node for exynos5420
ARM: EXYNOS: Add generic cluster power control functions
ARM: EXYNOS: use generic exynos cpu power control functions
ARM: EXYNOS: Add generic cpu power control functions for exynos SoCs
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "Samsung 2nd DT updates for v3.16" from Kukjin Kim:
exynos4
- add hsotg device, exynos_usbphy nodes
- add PMU syscon and audio subsystem nodes
- replace number by macro in clock binding
exynos4210-universal_c210
- add external sd card node and multimedia nodes
- enable USB functionality
exynos4412-trats2
- enable usb nodes and usb gagdet functionality
- add cm36651 light/proximity sensor node
- fixed gpio key node
exynos5250 and exynos5420
- add pmu syscon handle and sysreg system controller nodes
- add support for usb2phy
- replace number by macro in clock binding
- add USB 2.0 support on exynos5420
exynos5420-peach-pit
- move dp hpd gpio pin to pinctrl_0
* tag 'samsung-dt-2' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (21 commits)
ARM: dts: enable usb nodes for exynos4412-trats2
ARM: dts: add hsotg device node for exynos4
ARM: dts: add exynos_usbphy node for exynos4
ARM: dts: add PMU syscon node for exynos4
ARM: dts: add pmu syscon handle to exynos5420 hdmi
ARM: dts: add pmu syscon handle to exynos5250 hdmi
ARM: dts: replace number by macro in clock binding for exynos5420
ARM: dts: replace number by macro in clock binding for exynos5250
ARM: dts: replace number by macro in clock binding for exynos4
ARM: dts: add external sd card node for exynos4210-universal_c210
ARM: dts: add multimedia nodes for exynos4210-universal_c210
ARM: dts: enable USB functionality for exynos4210-universal_c210
ARM: dts: Enable USB gadget functionality for exynos4210-trats
ARM: dts: Add audio subsystem nodes to exynos4.dtsi
ARM: dts: fixed gpio key node for exynos4412-trats2
ARM: dts: add cm36651 light/proximity sensor node for exynos4412-trats2
ARM: dts: Add USB 2.0 support on exynos5420
ARM: dts: Add usb2phy support on exynos5420
ARM: dts: Add usb2phy to exynos5250
ARM: dts: Add sysreg sytem controller node to exynos5250 and exynos5420
...
irqchip core changes for v3.16 collected by Jason Cooper:
- irq-gic: Use a mask field
- irq-armada-370-xp: Move the DT binding docs to the irqchip directory
- irq-brcmstb-l2: New driver for Broadcom Set Top Box Level-2
Merge "ARM: berlin: DT changes for v3.16" from Sebastian Hesselbart:
Quite a lot changes but it looks like DT approach is really paying off.
BG2Q joins Berlin SoC family with corresponding development board, DW
gpio nodes for all SoCs. Most notably, we have settled clock bindings
to allow us to continue on drivers requiring clocks and pinctrl bindings.
Last but not least, BG2Q gained SDHCI support and is able to properly
boot into userspace.
* tag 'berlin-dt-3.16' of https://github.com/shesselba/linux-berlin:
ARM: dts: berlin: enable SD card reader and eMMC for the BG2Q DMP
ARM: dts: berlin: add the SDHCI nodes for the BG2Q
ARM: dts: berlin: add the pinctrl node and muxing setup for uarts
dt-binding: ARM: add pinctrl binding docs for Marvell Berlin2 SoCs
ARM: dts: berlin: convert BG2Q to DT clock nodes
ARM: dts: berlin: convert BG2 to DT clock nodes
ARM: dts: berlin: convert BG2CD to DT clock nodes
clk: berlin: add binding include for Berlin SoC clock ids
dt-binding: ARM: add clock binding docs for Marvell Berlin2 SoCs
ARM: dts: berlin: add the BG2CD GPIO nodes
ARM: dts: berlin: add the BG2 GPIO nodes
ARM: dts: berlin: add the BG2Q GPIO nodes
ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2Q
ARM: dts: berlin: add the Marvell BG2-Q DMP device tree
ARM: dts: berlin: add the Marvell Armada 1500 pro
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "ARM: omap l3-noc bus driver changes for v3.16 merge window, resend" from
Tony Lindgren:
Improvments to omap l3-noc bus driver for v3.16 merge window
to add support for am347x and dra7.
* tag 'omap-for-v3.16/l3-noc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits)
bus: omap_l3_noc: Add AM4372 interconnect error data
bus: omap_l3_noc: Add DRA7 interconnect error data
bus: omap_l3_noc: introduce concept of submodule
bus: omap_l3_noc: Add information about the context of operation
bus: omap_l3_noc: add information about the type of operation
bus: omap_l3_noc: ignore masked out unclearable targets
bus: omap_l3_noc: improve readability by using helper for slave event parsing
bus: omap_l3_noc: make error reporting and handling common
bus: omap_l3_noc: fix masterid detection
bus: omap_l3_noc: convert flagmux information into a structure
bus: omap_l3_noc: use of_match_data to pick up SoC information
bus: omap_l3_noc: Add support for discountinous flag mux input numbers
bus: omap_l3_noc: convert target information into a structure
bus: omap_l3_noc: move L3 master data structure out
bus: omap_l3_noc: un-obfuscate l3_targ address computation
bus: omap_l3_noc: switch over to relaxed variants of readl/writel
bus: omap_l3_noc: populate l3->dev and use it
bus: omap_l3_noc: remove iclk from omap_l3 struct
bus: omap_l3_noc: rename functions and data to omap_l3
bus: omap_l3_noc: Fix copyright information
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "ARM: omap dt changes for v3.16 merge window, part 2" From Tony Lindgren:
Device tree related changes for omaps.
* tag 'omap-for-v3.16/dt-part2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (49 commits)
ARM: dts: Enable mcpdm and mcbsp1 on DuoVero
ARM: dts: Convert DuoVero Parlor to use IOPAD macro
ARM: dts: am43xx: fix starting offset of NAND.filesystem MTD partition
ARM: dts: dra7: add support for parallel NAND flash
ARM: dts: am437x-gp-evm: Add ethernet support for GP EVM
ARM: dts: am4372: Add cpsw phy sel dt node
ARM: OMAP2+: Use pdata quirks for wl12xx on VAR-STK/DVK-OM44
ARM: dts: Add VAR-SOM-OM44 WLAN nodes
ARM: dts: Add support for OMAP4 VAR-DVK-OM44
ARM: dts: Add support for OMAP4 Variscite OM44 family
ARM: dts: Change IOPAD macro's for OMAP4/5
ARM: dts: AM33XX: fix ethernet and mdio default state
ARM: dts: am4372: Add hdq device tree data
ARM: omap2+: skip device build from platform code for dt
dts: dra7-evm: add USB support
ARM: dts: dra7: Add USB related nodes
ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gate
ARM: dts: omap4+: Add clocks to USB2 PHY node
ARM: dts: dra7: add OCP2SCP3 and SATA nodes
ARM: dts: omap5: add sata node
...
Signed-off-by: Olof Johansson <olof@lixom.net>
With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
The Cortex-A17 PMU is identical to that of the A12, so wire up a new
compatible string to the existing event structures.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Merge "Allwinner Core additions for 3.16, take 2" from Maxime Ripard:
- Convert the A31 SMP operations to the CPU_METHOD_OF_DECLARE mechanism
- Remove the reset code from the machine definition, that removes pretty much
all the code left in mach-sunxi
* tag 'sunxi-core-for-3.16-2' of https://github.com/mripard/linux:
ARM: sunxi: Remove init_machine callback
ARM: sunxi: Remove reset code from the platform
ARM: sun6i: Retire the smp field in A31 machine
Documentation: dt: bindings: Document Allwinner A31 enable method
ARM: sun6i: Use CPU_METHOD_OF_DECLARE
Documentation: dt: bindings: Document ARM PSCI enable method
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Patches from Anders Berg applied individually:
Here is version 4 of platform support for AXM5516 SoC.
The clk driver is now applied to clk-next. The rest should be ready for
arm-soc. Haven't got any response from the power/reset maintainers... I hope
this driver can be taken via arm-soc as well.
The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15
cores (in a 4x4 cluster configuration). The cores within each cluster share an
L2 cache, and the clusters are connected to each other via a CCN-504 cache
coherent interconnect.
This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located
above 4GB in the memory map.
* axxia/soc:
ARM: dts: axxia: Add reset controller
power: reset: Add Axxia system reset driver
ARM: axxia: Adding defconfig for AXM55xx
ARM: dts: Device tree for AXM55xx.
ARM: Add platform support for LSI AXM55xx SoC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15
cores (in a 4x4 cluster configuration). The cores within each cluster share an
L2 cache, and the clusters are connected to each other via a CCN-504 cache
coherent interconnect.
This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located
above 4GB in the memory map.
Signed-off-by: Anders Berg <anders.berg@lsi.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Samsung DT updates for v3.16
- exynos4
: add missing pinctrls
- exynos4412-trats2
: update camera nodes and add rear camera nodes
: rename alias for i2c_ak8975 label
Update camera nodes for exynos4 and exynos4412-trats2
- exynos5250
: update DWC3 usb controller and enable to use generic USB DRD phy
- exynos5250-snow
: enable dp-controller, fimd, hdmi and pwm backlight
: add sound node and Vbus regulator for USB 3.0
: add tps65090 power regulator
: add pinctrl for EC irq and i2c-arbitrator
- exynos5420
: change to correct compatible string for hdmi
: add PD entry to MFC codec and enable DWC3 and USB 3.0 PHY
: add MFC memory banks for smdk5420 and arndale-octa boards
- exynos5420-peach-pit
: add support exynos5420 based peach-pit board
: add sound node and Vbus regulatro for USB 3.0
: enable dp-controller, fimd
- exynos5420-smdk5420
: add Vbus regulatro for USB 3.0
- use generic DT bindings for map SYSRAM
[olof: Fixed up conflict with a fix for 4212 secondary CPU startup, carrying
over the fix to the reworked code]
* tag 'samsung-dt' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (32 commits)
ARM: dts: Add MFC memory banks to exynos5420 boards
ARM: dts: enable dp-controller for exynos5420-peach-pit board
ARM: dts: enable fimd for exynos5420 based peach-pit board
ARM: dts: enable dp-controller for exynos5250-snow board
ARM: dts: enable fimd for exynos5250-snow board
ARM: dts: enable pwm backlight for exynos5250-snow
ARM: dts: Add pwmX_out pinctrl nodes to exynos5250
ARM: dts: Add Vbus regulator for USB 3.0 on exynos5420-smdk5420
ARM: dts: Add Vbus regulator for USB 3.0 on exynos5420-peach-pit
ARM: dts: Add Vbus regulator for USB 3.0 on exynos5250-snow
ARM: dts: Add PD entry to MFC codec on exynos5420
ARM: dts: Add sound node for exynos5420-peach-pit board
ARM: dts: Add sound node for exynos5250-snow board
ARM: dts: Update DWC3 usb controller to use new phy driver for exynos5250
ARM: dts: Enable support for generic USB DRD phy for exynos5250
ARM: dts: Enable support for DWC3 controller for exynos5420
ARM: dts: Enable support for USB 3.0 PHY controller for exynos5420
ARM: dts: enable hdmi for exynos5420-peach-pit board
ARM: dts: change to correct compatible string for exynos5420 hdmi
ARM: dts: enable hdmi for exynos5250 based snow board
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds sysreg-syscon node to exynos5250 and exynos5420 device
tree, to access System Register's registers using syscon driver.
Signed-off-by: Kamil Debski <k.debski@samsung.com>
[gautam.vivek@samsung.com: Split this syreg-syscon dts entry]
[gautam.vivek@samsung.com: added similar syscon entry for exynos5420]
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
[vikas.sajjan@samsung.com: updated the binding document]
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Merge "ARM: STi: SoC changes for v3.16" from Maxime Coquelin:
SoC changes for STi platforms
- Add support for STiH407
* tag 'sti-soc-for-v3.16' of git://git.stlinux.com/devel/kernel/linux-sti:
ARM: STi: Add STiH407 SoC support
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "ARM: rockchip: devicetree changes for v3.16" from Heiko Stübner:
Addition of missing board compatible names and their vendor-prefixes
as well as the dts portions of the pinctrl rework.
* tag 'v3.16-rockchip-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
ARM: dts: rockchip: convert pinctrl nodes to new bindings
ARM: dts: rockchip: add root compatible properties
of: add mundoreader and radxa vendor prefixes
Signed-off-by: Olof Johansson <olof@lixom.net>
Merge "ARM: mvebu: SoC changes for v3.16" from Jason Cooper:
mvebu SoC changes for v3.16
- Armada 375/38x coherency support
- Armada 375/38x SMP support
- mvebu PMSU and CPU reset support
- Armada 370/XP cpuidle support
- kirkwood remove platform init of audio device
- small fixes and cleanup for new SoC (375/38x)
Note:
- due to complex deps, cpuidle changes Acked by appropriate maintainer for
going though arm-soc tree.
* tag 'mvebu-soc-3.16' of git://git.infradead.org/linux-mvebu: (46 commits)
ARM: mvebu: Fix pmsu compilation when ARMv6 is selected
ARM: mvebu: conditionalize Armada 375 coherency workaround
ARM: mvebu: conditionalize Armada 375 SMP workaround
ARM: mvebu: add Armada 375 A0 revision definition
ARM: mvebu: initialize mvebu-soc-id earlier
ARM: mvebu: fix thermal quirk SoC revision check
ARM: Kirkwood: t5325: Remove platform device to instantiate audio
ARM: Kirkwood: Remove platform driver for codec
ARM: mvebu: Add thermal quirk for the Armada 375 DB board
ARM: mvebu: Select HAVE_ARM_TWD only if SMP is enabled
ARM: mvebu: fix the name of the parameter used in mvebu_get_soc_id
ARM: mvebu: remove unnecessary ifdef around l2x0_of_init
ARM: mvebu: register the cpuidle driver for the Armada XP SoCs
cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC
ARM: mvebu: Register notifier callback for the cpuidle transition
ARM: mvebu: refine which files are build in mach-mvebu
ARM: mvebu: Add the PMSU related part of the cpu idle functions
ARM: mvebu: Allow to power down L2 cache controller in idle mode
ARM: mvebu: Low level function to disable HW coherency support
ARM: mvebu: Split low level functions to manipulate HW coherency
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Add pin control binding documentation to the SoC binding documentaion
as pinctrl is part of chip/system control registers. The documentation
also explains how to configure this group based controller.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This adds mandatory device tree binding documentation for the clock related
IP found on Marvell Berlin2 (BG2, BG2CD, and BG2Q) SoCs to the Berlin SoC
binding documentation.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family).
The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local
timer, apb timers and uarts for now. Also add corresponding binding documentation.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Merge "dts: socfpga: general updates for the socfpga platform" from Dinh
Nguyen:
Mostly DTS additions to the SOCFPGA platform from Steffan Trumtrar, and a
couple of device tree documentation updates/typo fix.
This one does not the GPIO binding patch, as that is pending further
discussion. Also, v3 fixes a rebase artifact and compile tested.
* tag 'socfpga-dt-updates-for-3.16_v3' of git://git.rocketboards.org/linux-socfpga-next:
ARM: socfpga: dts: Add div-reg to the main_pll clocks
ARM: socfpga: dts: add reset-controller
Documentation: dt: reset: move socfpga-reset
Documentation: dt: socfpga: add reset-cells property
ARM: socfpga: dts: Add DTS entries for USB
ARM: socfpga: dts: Remove hard coded clock-frequency property
ARM: socfpga: dts: add eeprom and rtc on i2c0
ARM: socfpga: dts: convert to preprocessor includes
ARM: socfpga: dts: add rtc on i2c0 to socrates
ARM: socfpga: dts: add support for EBV SOCrates
ARM: socfpga: dts: add can0+1
ARM: socfpga: dts: add i2c busses
ARM: socfpga: dts: add remaining interrupts for pdma
ARM: socfpga: dts: fix pdma interrupt
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch - finally, after over 6 months! :-( - addresses
Samuel's request to split the vexpress-sysreg driver into
smaller portions and define the device in a form of MFD
cells:
* LEDs code has been completely removed and replaced with
"gpio-leds" nodes in the tree (referencing dedicated
GPIO subnodes in sysreg - bindings documentation updated);
this also better fits the reality as some variants of the
motherboard don't have all the LEDs populated
* syscfg bridge code has been extracted into a separate
driver (placed in drivers/misc for no better place)
* all the ID & MISC registers are defined as sysconf
making them available for other drivers should they need
to use them (and also to the user via /sys/kernel/debug/regmap
which can be helpful in platform debugging)
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Components of the Versatile Express platform (configuration
microcontrollers on motherboard and daughterboards in particular)
talk to each other over a custom configuration bus. They
provide miscellaneous functions (from clock generator control
to energy sensors) which are represented as platform devices
(and Device Tree nodes). The transactions on the bus can
be generated by different "bridges" in the system, some
of which are universal for the whole platform (for the price
of high transfer latencies), others restricted to a subsystem
(but much faster).
Until now drivers for such functions were using custom "func"
API, which is being replaced in this patch by regmap calls.
This required:
* a rework (and move to drivers/bus directory, as suggested
by Samuel and Arnd) of the config bus core, which is much
simpler now and uses device model infrastructure (class)
to keep track of the bridges; non-DT case (soon to be
retired anyway) is simply covered by a special device
registration function
* the new config-bus driver also takes over device population,
so there is no need for special matching table for
of_platform_populate nor "simple-bus" hack in the arm64
model dtsi file (relevant bindings documentation has
been updated); this allows all the vexpress devices
fit into normal device model, making it possible
to remove plenty of early inits and other hacks in
the near future
* adaptation of the syscfg bridge implementation in the
sysreg driver, again making it much simpler; there is
a special case of the "energy" function spanning two
registers, where they should be both defined in the tree
now, but backward compatibility is maintained in the code
* modification of the relevant drivers:
* hwmon - just a straight-forward API change
* power/reset driver - API change
* regulator - API change plus error handling
simplification
* osc clock driver - this one required larger rework
in order to turn in into a standard platform driver
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Acked-by: Mark Brown <broonie@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Mike Turquette <mturquette@linaro.org>
The PSCI v0.2+ spec defines standard values for PSCI function IDs.
Add a new binding entry so that pre v0.2 implementations can
use DT entries for function IDs and v0.2+ implementations use
standard entries as defined by the PSCIv0.2 specification.
Signed-off-by: Ashwin Chaugule <ashwin.chaugule@linaro.org>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Add the missing 'compatible' property to device tree root node of
- rk3066a-bqcurie2.dts
- rk3188-radxarock.dts
and document the new values.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
DRA722 is part of DRA72x family which are single core cortex A15 devices
with most infrastructure IPs otherwise same as whats on the DRA74x family.
So move the cpu nodes into dra74x.dtsi and dra72x.dtsi respectively.
Also add a minimal dra72-evm dts file.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: linux-doc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Acked-by: Arnd Bergmann <arnd@arndb.de>
[tony@atomide.com: updated for Makefile sorting]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Instead of having the documentation for the socfpga-reset controller in a
vendor specific directory, move it to the reset folder to all the other
reset drivers.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
To be able to use the reset-controller framework, the property
#reset-cells
is mandatory.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Add AM4372 information to handle L3 error.
AM4372 has two clk domains 100f and 200s. Provide flagmux and data
associated with it.
NOTE: Timeout doesn't have STDERRLOG_MAIN register. And per hardware
team, L3 timeout error cannot be cleared the normal way (by setting
bit 31 in STDERRLOG_MAIN), instead it may be required to do system
reset. L3 error handler can't help in such scenarios.
Hence indicate timeout target offset as L3_TARGET_NOT_SUPPORTED as
done for undocumented bits.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Afzal Mohammed <afzal@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
DRA7 is distinctly different from OMAP4 in terms of masters and clock
domain organization. There two main clock domains which is divided as
follows:
<0x44000000 0x1000000> is clk1 and clk2 is the sub clock domain
<0x45000000 0x1000> is clk3
Add all the data needed to handle L3 error handling on DRA7 devices
and mark clk2 as subdomain and provide a compatible flag for
functionality. Other than the data difference the hardware blocks
involved are essentially the same.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[nm@ti.com: bugfixes and generic improvements, documentation]
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Darren Etheridge <detheridge@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
clockevent fixes for 3.15 from Daniel Lezcano:
* Lorenzo Pieralizi fixed an issue with the arch_arm_timer where the
C3STOP flag for all the arch can cause some trouble by setting the
flag only if the power domain is not always on
* Alexander Shiyan fixed a compilation by changing the init function
to the right prototype
ARM arch timers are tightly coupled with the CPU logic and lose context
on platform implementing HW power management when cores are powered
down at run-time. Marking the arch timers as C3STOP regardless of power
management capabilities causes issues on platforms with no power management,
since in that case the arch timers cannot possibly enter states where the
timer loses context at runtime and therefore can always be used as a high
resolution clockevent device.
In order to fix the C3STOP issue in a way compliant with how real HW
works, this patch adds a boolean property to the arch timer bindings
to define if the arch timer is managed by an always-on power domain.
This power domain is present on all ARM platforms to date, and manages
HW that must not be turned off, whatever the state of other HW
components (eg power controller). On platforms with no power management
capabilities, it is the only power domain present, which encompasses
and manages power supply for all HW components in the system.
If the timer is powered by the always-on power domain, the always-on
property must be present in the bindings which means that the timer cannot
be shutdown at runtime, so it is not a C3STOP clockevent device.
If the timer binding does not contain the always-on property, the timer is
assumed to be power-gateable, hence it must be defined as a C3STOP
clockevent device.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Magnus Damm <damm@opensource.se>
Cc: Marc Carino <marc.ceeeee@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The Armada 370 and Armada XP have registers that allow to reset the
CPUs, which is particularly useful to take the secondary CPUs out of
reset in the context of the SMP support.
Unfortunately, an implementation mistake was originally made and the
support for these registers was integrated into the PMSU driver, which
is in fact completely unrelated. And it turns out that the Armada 375
has the same CPU reset registers, but does not have the PMSU
registers.
Therefore, this commit creates a small CPU reset driver. All it does
is provide a simple mvebu_cpu_reset_deassert() function that the SMP
support code can call to take secondary CPUs out of reset. As of this
commit, the driver isn't being used, it will be used through changes
in the following commits.
Note that we initially planned to use the 'reset controller'
framework, but it requires the addition of "resets" properties in the
Device Tree, which are causing too many problems if we want to keep
the Device Tree backward compatibility. Moreover, the 'reset
controller' framework is mainly useful when a device driver needs to
request a reset of its device from a separate reset controller. In our
case, the CPU reset handling and the SMP core code are both located in
arch/arm/mach-mvebu/ and are tightly linked together, so there's no
real benefit in going through a separate framework.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483433-25836-2-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The Armada 375, like the Armada 370 and Armada XP, has a coherency
unit. However, unlike the coherency unit of 370/XP which does both CPU
and I/O coherency, the one on Armada 735 only does I/O
coherency. Therefore, instead of having two sets of registers (the
first one being used mainly to register each CPU in the coherency
fabric, the second one being used for the I/O coherency barrier), it
has only one set of register (for the I/O coherency barrier).
This commit adds a new "marvell,armada-375-coherency-fabric"
compatible string for this variant of the coherency fabric. The custom
DMA operations, and the way of triggering an I/O barrier is the same
as Armada 370/XP, so the code changes are minimal. However, the
set_cpu_coherent() function is not needed on Armada 375 and will not
work.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1397483228-25625-7-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
