Commit Graph

8 Commits

Author SHA1 Message Date
Benjamin Herrenschmidt
6aff0bf641 ftgmac100: Disable HW checksum generation on AST2400, enable on others
We found out that HW checksum generation only works from AST2500
onward. This disables it on AST2400 and removes the "no-hw-checksum"
properties in the device-trees. The problem we had wasn't related
to NC-SI.

Also rework the logic testing for that property so it can be used
to disable HW checksum generation and checking regardless of whether
NC-SI is used or not in case other variants out there need this.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-12 10:17:01 -04:00
Benjamin Herrenschmidt
78d28543a6 ftgmac100: Use device "compatible" property, not machine.
We test for aspeed chips to handle a couple of special cases,
but we do that by checking the machine type which isn't right.

Instead check the actual device compatible property. This also
updates the dtsi files for the aspeed SoC to match.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
2017-04-12 10:17:01 -04:00
Joel Stanley
34ea5c9de3 ARM: dts: aspeed: Add ftgmac100 to g4 and g5 platforms
Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10 21:55:43 +11:00
Andrew Jeffery
2039f90d13 ARM: dts: aspeed-g5: Add gpio controller to devicetree
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10 21:55:35 +11:00
Andrew Jeffery
b590c8d2ee ARM: dts: aspeed-g5: Add syscon and pin controller nodes
The pin controller's child nodes expose the functions currently
implemented in the g5 pin controller driver.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10 21:55:31 +11:00
Andrew Jeffery
cec822f89e ARM: dts: aspeed-g5: Add LPC Controller node
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10 21:55:21 +11:00
Andrew Jeffery
daf042580a ARM: dts: aspeed-g5: Add SoC Display Controller node
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
2017-01-10 21:55:19 +11:00
Joel Stanley
0244062265 arm/dst: Add Aspeed ast2500 device tree
This adds a common device tree for all fifth generation Aspeed systems,
and a board specific device tree for the ast2500 evaluation board.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2016-05-09 17:41:58 +09:30