Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts and
generates an error:
genirq: Setting trigger mode 0 for irq 16 failed (gic_set_type+0x0/0x68)
The GIC requires shared interrupts to be edge rising or level high.
Platform declares support for both. Arbitrarily choose level high
everywhere hoping it will work on each platform.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reported-by: Alban Browaeys <alban.browaeys@gmail.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Add a device node for the RST module, which provides a.o. reset control
and mode pin monitoring.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
There are no boards in mainline using exynos4415.dtsi. These DTSIs
were not tested for long. I am also not aware of any popular out-of-tree
boards using this (except consumer devices released by Samsung but those
cannot use mainline).
Keeping Exynos4415 costs some useless effort so remove it.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Therefore aligning the panel nodes name across all platforms.
Also removing the bt_rfkill node since the mainline rfkill-gpio driver
doesn't support device trees.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
With commit 851ce93224 ("usb: chipidea: otg: don't wait vbus
drops below BSV when starts host"), the driver can support
enabling vbus output without software control, so this board
(control vbus output through ID pin) can support dual-role now.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add a syscon node for the SoC CFGCHIPn registers. It includes a child node
for the USB PHY that is part of this range of registers.
Signed-off-by: David Lechner <david@lechnology.com>
[nsekhar@ti.com: drop OF_DEV_AUXDATA() addition]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
i.MX31 Clock Control Module controller is found on AIPS2 bus, move it
there from SPBA bus to avoid a conflict of device IO space mismatch.
Fixes: ef0e4a606f ("ARM: mx31: Replace clk_register_clkdev with clock DT lookup")
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The type of AVIC interrupt controller found on i.MX31 is one-cell,
namely 31 for CCM DVFS and 53 for CCM, however for clock control
module its interrupts are specified as 3-cells, fix it.
Fixes: ef0e4a606f ("ARM: mx31: Replace clk_register_clkdev with clock DT lookup")
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The address of the mailbox node in the bcm283x.dtsi also has a typo.
So fix it accordingly.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Fixes: 05b682b7a3 ("ARM: bcm2835: dt: Add the mailbox to the device tree")
Signed-off-by: Eric Anholt <eric@anholt.net>
Add pins used by the LCD controller and a disabled LCDC node to be
reused in device trees including da850.dtsi.
Signed-off-by: Karl Beldan <kbeldan@baylibre.com>
[Bartosz:
- added the commit description
- changed the dt node name to a generic one
- added a da850-specific compatible string
- removed the tilcdc,panel node
- moved the pins definitions to da850.dtsi as suggested by
Sekhar Nori (was in: da850-lcdk.dts)]
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: fix compatible property and remove interrupt-parent]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Mostly simple overlapping changes.
For example, David Ahern's adjacency list revamp in 'net-next'
conflicted with an adjacency list traversal bug fix in 'net'.
Signed-off-by: David S. Miller <davem@davemloft.net>
ARMv7 Vexpress DT fixes/updates for v4.10
1. Addition of CPU dmips/capacity information to TC2 platform
2. Cleanup/fix unit address warnings and removal of skeleton.dtsi from
MPS2 device tree
* tag 'vexpress-dt-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
ARM: dts: vexpress: add TC2 cpu capacity-dmips-mhz information
ARM: dts: mps2: remove skeleton.dtsi include and fix unit address warnings
Signed-off-by: Olof Johansson <olof@lixom.net>
The i.MX fixes for 4.9:
- A couple of patches from Fabio to fix the GPC power domain regression
which is caused by PM Domain core change 0159ec6707
("PM / Domains: Verify the PM domain is present when adding a
provider"), and a related kernel crash seen with multi_v7_defconfig
build.
- Correct the PHY ID mask for AR8031 to match phy driver code.
- Apply new added timer erratum A008585 for LS1043A and LS2080A SoC.
- Correct vf610 global timer IRQ flag to avoid warning from gic driver
after commit 992345a58e ("irqchip/gic: WARN if setting the
interrupt type for a PPI fails").
* tag 'imx-fixes-4.9' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: mach-imx6q: Fix the PHY ID mask for AR8031
ARM: dts: vf610: fix IRQ flag of global timer
ARM: imx: gpc: Fix the imx_gpc_genpd_init() error path
ARM: imx: gpc: Initialize all power domains
arm64: dts: Add timer erratum property for LS2080A and LS1043A
Signed-off-by: Olof Johansson <olof@lixom.net>
There's a cognitive load to figure out which mmc device node corresponds
to the eMMC flash, uSD card and WiFI SDIO module on the Snow, Peach Pi
and Pit boards.
So it's better to have comments in the DTS to make this more clear.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
[krzk: Squashed three patches into one]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
SoCFPGA DTS update for v4.10, part 1
- Add a Macnica sodia board
- Add support for the Arria10 System resource device
- Add support for the Arria10 LEDs
- Add QSPI to the socrates board
- Update L2 cache settings, enabling arm,shared-override
* tag 'socfpga_dts_for_v4.10_part_1' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: socrates: enable qspi
ARM: dts: socfpga: add qspi node
ARM: dts: socfpga: Add LED framework to A10-SR GPIO
ARM: dts: socfpga: Enable GPIO parent for Arria10 SR chip
ARM: dts: socfpga: Add Devkit A10-SR fields for Arria10
ARM: dts: socfpga: Add SPI Master1 for Arria10 SR chip
ARM: dts: socfpga: enable arm,shared-override in the pl310
ARM: dts: socfpga: Add Macnica sodia board
ARM: dts: socfpga: Add new MCVEVK manufacturer compat
Signed-off-by: Olof Johansson <olof@lixom.net>
The change setup the peripheral clock (PERIPH_CLK) as the default
parent clock for PWM1 & PWM2.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
When the patch is applied, the allwinner,driver and allwinner,pull
properties are removed.
Although they're described to be optional in the devicetree binding,
without them, the pinmux cannot be initialized, and the uart cannot
be used.
Add them back to fix the problem, and makes the bluetooth on iNet D978
Rev2 board work.
Fixes: 82eec38424 (ARM: dts: sun8i: add pinmux for UART1 at PG)
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
liteBoard is a development board which uses liteSOM as its base.
Hardware specification:
* liteSOM (i.MX6UL, DRAM, eMMC)
* Ethernet PHY (id 0)
* USB host (usb_otg1)
* MicroSD slot (uSDHC1)
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This is a SOM (System on Module), so it will be part of another boards.
Hence, this is a "dtsi" file that will be included from another device
tree files.
Hardware specification:
* Freescale i.MX6UL SoC
* up to 512 MB RAM
* eMMC on uSDHC2
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The global timer IRQ (PPI[0], PPI 11 in device tree terms) is a
rising edge interrupt. The ARM Cortex-A5 MPCore TRM in Chapter
10.1.2. Interrupt types and sources says:
"Interrupt is rising-edge sensitive."
The bits seem to be read-only, hence this missconfiguration had
no negative effect. However, with commit 992345a58e
("irqchip/gic: WARN if setting the interrupt type for a PPI fails")
warnings such as this get printed:
GIC: PPI11 is secure or misconfigured
With this change the new configuration matches the default
configuration and no warning is printed anymore.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add initial device trees for UDOO Neo Basic, Extended and Full boards:
* Serial console is enabled, other serial ports are prepared.
* I2C based PMIC is enabled.
* Ethernet is enabled for Basic and Full.
* SDHC is enabled, with the SDIO_PWR GPIO modeled as a regulator.
* Both user LEDs are enabled, with the orange one reserved for the M4
and with the SD card as default trigger for the red LED.
The decision on a board compatible string is deferred to later.
Cc: Ettore Chimenti <ettore.chimenti@udoo.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The LCDIF interrupt should be triggered by the rising edge of the
IRQ line because we only want the interrupt to trigger once per each
frame. It seems the LCDIF IRQ line cannot be explicitly de-asserted
by software, so the previous behavior before this patch, where the
interrupt was triggered by level-high status of the IRQ line, caused
the interrupt to fire again immediatelly after it was handled, which
caused the system to lock up due to the high rate of interrupts.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
