6 Commits

Author	SHA1	Message	Date
Ben Skeggs	4cddeb9b31	drm/nouveau/disp/sor/gf119-: add method to program mst payload information ... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>	2016-11-07 14:04:42 +10:00
Ben Skeggs	f2a4051379	drm/nouveau/disp/sor/gf119-: add method to control mst enable ... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>	2016-11-07 14:04:42 +10:00
Ben Skeggs	217215041b	drm/nouveau/disp/sor/gf119: select correct sor when poking training pattern ... Fixes a regression caused by a stupid thinko from "disp/sor/gf119: both links use the same training register". Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org	2016-07-06 06:56:37 +10:00
Ben Skeggs	4691409b3e	drm/nouveau/disp/sor/gm107: training pattern registers are like gm200 ... Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org	2016-06-07 08:11:25 +10:00
Ben Skeggs	a8953c52b9	drm/nouveau/disp/sor/gf119: both links use the same training register ... It appears that, for whatever reason, both link A and B use the same register to control the training pattern. It's a little odd, as the GPUs before this (Tesla/Fermi1) have per-link registers, as do newer GPUs (Maxwell). Fixes the third DP output on NVS 510 (GK107). Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Cc: stable@vger.kernel.org	2016-06-07 08:11:14 +10:00
Ben Skeggs	2a7909c0ad	drm/nouveau/disp: split user classes out from engine implementations ... Signed-off-by: Ben Skeggs <bskeggs@redhat.com>	2015-08-28 12:40:40 +10:00