Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same.
Current PFC driver is very difficult to read, because macro names are
using different length.
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
PINMUX_IPSR_MODSEL_DATA(ipsr, ...)
It can be readable if we can use PINMUX_IPSR_MSEL() instead
of PINMUX_IPSR_MODSEL_DATA()
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same.
Current PFC driver is very difficult to read, because macro names are
using different length.
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
PINMUX_IPSR_MODSEL_DATA(ipsr, ...)
It can be readable if we can use PINMUX_IPSR_MSEL() instead
of PINMUX_IPSR_MODSEL_DATA()
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same.
Current PFC driver is very difficult to read, because macro names are
using different length.
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
PINMUX_IPSR_MODSEL_DATA(ipsr, ...)
It can be readable if we can use PINMUX_IPSR_MSEL() instead
of PINMUX_IPSR_MODSEL_DATA()
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same.
Current PFC driver is very difficult to read, because macro names are
using different length.
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
PINMUX_IPSR_MODSEL_DATA(ipsr, ...)
It can be readable if we can use PINMUX_IPSR_MSEL() instead
of PINMUX_IPSR_MODSEL_DATA()
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Now, PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA() are same.
Current PFC driver is very difficult to read, because macro names are
using different length.
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
PINMUX_IPSR_MODSEL_DATA(ipsr, ...)
It can be readable if we can use PINMUX_IPSR_MSEL() instead
of PINMUX_IPSR_MODSEL_DATA()
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
The difference between PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA()
are FN_xxx order, and PINMUX_IPSR_MSEL() is used only from r8a7778.
Now it r8a7778 works correctly with PINMUX_IPSR_MODSEL_DATA() order.
This means we can merge PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA().
Current PFC driver is very difficult to read, because macro names are
using different length. Especially PINMUX_IPSR_MODSEL_DATA() is well
used macro
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
PINMUX_IPSR_MODSEL_DATA(ipsr, ...)
It can be readable if we can merge
PINMUX_IPSR_MSEL() and PINMUX_IPSR_MODSEL_DATA()
PINMUX_IPSR_NOGP(ispr, ...)
PINMUX_IPSR_DATA(ipsr, ...)
PINMUX_IPSR_NOGM(ispr, ...)
PINMUX_IPSR_NOFN(ipsr, ...)
PINMUX_IPSR_MSEL(ipsr, ...)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Shmobile is all multiplatform these days, so get rid of the reference to
CONFIG_ARCH_SHMOBILE_LEGACY.
Move the legacy code to do the non-DT mapping between GPIOs and pins
inside the existing #ifdef CONFIG_SUPERH section.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
When using serial port SCIFB1_B, transmit works, but nothing is
received.
Receive fails because the SCIFB1_SCK_B settings configure the wrong
value for the sel_scifb1 field in the Module Select Register (MOD_SEL),
due to an ambiguity in the R-Car M2-W and M2-N datasheets.
Tested on r8a7791/koelsch using pins 53 (TXD) and 72 (RXD) on EXIO
Connector A.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
SCIF0 on R-Car E2 does not have an SCK pin.
"SCIF_CLK" is the (H)SCIF baud rate generation clock pin, which is not
yet supported.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Legacy function GPIOs are no longer used on ARM since commit
a27c5cd1a0 ("sh-pfc: sh73a0: Remove function GPIOs").
Extract its setup code into a separate function, and make all function
GPIO related code and data depend on CONFIG_SUPERH.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
On platforms where the PFC/GPIO controller is instantiated from DT, the
mapping between GPIOs and pins is set up using the "gpio-ranges"
property in DT.
Hence stop setting up the mapping from C code on DT platforms.
This code is still used for SH or ARM-legacy platforms.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
The mediatek pinctrl driver uses the BIT() macro instead of open
coding 1 << n in all but one place. Replace this occurrence with
the BIT() macro for consistency.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pull irq updates from Thomas Gleixner:
"This is a rather large update post rc1 due to the final steps of
cleanups and API changes which had to wait for the preparatory patches
to hit your tree.
- Regression fixes for ARM GIC irqchips
- Regression fixes and lockdep anotations for renesas irq chips
- The leftovers of the cleanup and preparatory patches which have
been ignored by maintainers
- Final conversions of the newly merged users of obsolete APIs
- Final removal of obsolete APIs
- Final removal of ARM artifacts which had been introduced during the
conversion of ARM to the generic interrupt code.
- Final split of the irq_data into chip specific and common data to
reflect the needs of hierarchical irq domains.
- Treewide removal of the first argument of interrupt flow handlers,
i.e. the irq number, which is not used by the majority of handlers
and simple to retrieve from the other argument the irq descriptor.
- A few comment updates and build warning fixes"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits)
arm64: Remove ununsed set_irq_flags
ARM: Remove ununsed set_irq_flags
sh: Kill off set_irq_flags usage
irqchip: Kill off set_irq_flags usage
gpu/drm: Kill off set_irq_flags usage
genirq: Remove irq argument from irq flow handlers
genirq: Move field 'msi_desc' from irq_data into irq_common_data
genirq: Move field 'affinity' from irq_data into irq_common_data
genirq: Move field 'handler_data' from irq_data into irq_common_data
genirq: Move field 'node' from irq_data into irq_common_data
irqchip/gic-v3: Use IRQD_FORWARDED_TO_VCPU flag
irqchip/gic: Use IRQD_FORWARDED_TO_VCPU flag
genirq: Provide IRQD_FORWARDED_TO_VCPU status flag
genirq: Simplify irq_data_to_desc()
genirq: Remove __irq_set_handler_locked()
pinctrl/pistachio: Use irq_set_handler_locked
gpio: vf610: Use irq_set_handler_locked
powerpc/mpc8xx: Use irq_set_handler_locked()
powerpc/ipic: Use irq_set_handler_locked()
powerpc/cpm2: Use irq_set_handler_locked()
...
Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.
Remove the argument.
Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Julia Lawall <Julia.Lawall@lip6.fr>
Cc: Jiang Liu <jiang.liu@linux.intel.com>
?SYNTAX ERROR
irq_desc_get_irq_chip() does not exist. It should
be irq_desc_get_chip(). Tested by compiling
s3c2410_defconfig.
Cc: Thomas Gleixner <tglx@linutronix.de>
Reported-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If the gpio driver is confused about the numbers for gpio-ranges,
pinctrl_ready_for_gpio_range() may get called with invalid GPIO
causing a NULL pointer exception. Let's instead provide a warning
that allows fixing the problem and return with error.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since commit 323de9efdf ("pinctrl: make pinctrl_register() return proper
error code"), pinctrl_register returns an error code rather than NULL on
failure. Update a driver that was introduced more recently.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@@
expression e,e1,e2;
@@
e = pinctrl_register(...)
... when != e = e1
if (
- e == NULL
+ IS_ERR(e)
) {
...
return
- e2
+ PTR_ERR(e)
;
}
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Since commit 323de9efdf ("pinctrl: make pinctrl_register() return proper
error code"), pinctrl_register returns an error code rather than NULL on
failure. Update some drivers that were introduced more recently.
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@@
expression e,e1,e2;
@@
e = pinctrl_register(...)
... when != e = e1
if (
- e == NULL
+ IS_ERR(e)
) {
...
return
- e2
+ PTR_ERR(e)
;
}
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.3 development
cycle.
Like with GPIO it's a lot of stuff. If my subsystems are any sign of
the overall tempo of the kernel v4.3 will be a gigantic diff.
[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
we'll see - Linus ]
Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing all
call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a combined
call to irq_set_chained_handler_and_data(). This series was
created by Thomas Gleixner after the problem was observed by
Russell King.
- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which is
way cleaner.
- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs from
IRQ numbers. The goal is to get rid of the irq number from the
handlers in the IRQ flow which is nice.
Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
in IRQ handlers to play nice with the realtime patch set.
- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
ProXtream2 and PH1-LD6b SoC pin control support.
- Reverse-egineered the S/PDIF settings for the Allwinner sun4i
driver.
- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC subdrivers"
* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
pinctrl: at91: fix null pointer dereference
pinctrl: mediatek: Implement wake handler and suspend resume
pinctrl: mediatek: Fix multiple registration issue.
pinctrl: sh-pfc: r8a7794: add USB pin groups
pinctrl: at91: Use generic irq_{request,release}_resources()
pinctrl: cherryview: Use raw_spinlock for locking
pinctrl: baytrail: Use raw_spinlock for locking
pinctrl: imx6ul: Remove .owner field
pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pinctrl: sun4i: add spdif to pin description.
pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
pinctrl: baytrail: Serialize all register access
pinctrl: baytrail: Drop FSF mailing address
pinctrl: rockchip: only enable gpio clock when it setting
pinctrl/mediatek: fix spelling mistake in dev_err error message
pinctrl: cherryview: Serialize all register access
pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
pinctrl: nomadik: reflect current input value
...
Pull ARM DT updates from Olof Johansson:
"Ladies and gentlemen, we proudly announce to you the latest branch of
ARM device tree contents for the mainline kernel. Come and see, come
and see!
No less than twentythree thousand lines of additions! Just imagine the
joy you will have of using your mainline kernel on newly supported
hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or
UniPhier hardware!
For those of you feeling less adventurous, added hardware support on
platforms such as TI DM814x and Gumstix Overo platforms might be more
of your liking.
We've got something for everyone here!
Ahem. Cough. So, anyway...
This is the usual large batch of DT updates. Lots and lots of smaller
changes, some of the larger ones to point out are:
- Rockchip veyron (Chromebook) support, as well as several other new boards
- DRM support on Atmel AT91SAM9N12EK
- USB additions on some Allwinner platforms
- Mediatek MT6580 support
- Freescale i.MX6UL support
- cleanups for Renesas shmobile platforms
- lots of added devices on LPC18xx
- lots of added devices and boards on UniPhier
There's also some dependent code added here, in particular some
branches that are primarily merged through the clock tree"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits)
ARM: tegra: Add gpio-ranges property
ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
ARM: tegra: Add Tegra124 PMU support
ARM: tegra: jetson-tk1: Add GK20A GPU DT node
ARM: tegra: venice2: Add GK20A GPU DT node
ARM: tegra: Add IOMMU node to GK20A
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Enable the DFLL on the Jetson TK1
ARM: tegra: Add the DFLL to Tegra124 device tree
ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
ARM: dts: rockchip: correct regulator power states for suspend
ARM: dts: rockchip: correct regulator PM properties
ARM: dts: vexpress: Use assigned-clock-parents for sp810
pinctrl: tegra: Only set the gpio range if needed
arm: boot: dts: am4372: add ARM timers and SCU nodes
ARM: dts: AM4372: Add the am4372-rtc compatible string
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
...
Since our common driver need support main chip and PMU
at the same time, that means it will register two
pinctrl device, and the pinctrl_desc structure should
be used two times.
But pinctrl_desc use global static definition, then
the latest registered pinctrl device will overwrite
the old one's, all members in pinctrl_desc will set to
the new one's, such as name, pins and pins numbers, etc.
This is a bug.
Move pinctrl_desc into mtk_pinctrl, assign new value for
each pinctrl device to fix it.
Cc: stable@vger.kernel.org # v4.1+
Signed-off-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
Reviewed-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The at91-specific irq_{request,release}_resources() callbacks are
identical to the generic ones, modulo the bug fix in 5b76e79c77
("gpiolib: irqchip: prevent driver unloading if gpio is used as irq
only").
Until commit 8b67a1f0ad ("gpio: don't override irq_*_resources()
callbacks"), the buggy at91-specific callbacks were never used, though.
Hence drop the at91-specific ones in favor of the generic ones.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
When running -rt kernel and an interrupt happens on a GPIO line controlled by
Intel Cherryview/Braswell pinctrl driver we get:
BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
Preemption disabled at:[<ffffffff81092e9f>] cpu_startup_entry+0x17f/0x480
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #16
...
Call Trace:
<IRQ> [<ffffffff816283c6>] dump_stack+0x4a/0x61
[<ffffffff81077e17>] ___might_sleep+0xe7/0x170
[<ffffffff8162d6cf>] rt_spin_lock+0x1f/0x50
[<ffffffff812e52ed>] chv_gpio_irq_ack+0x3d/0xa0
[<ffffffff810a72f5>] handle_edge_irq+0x75/0x180
[<ffffffff810a3457>] generic_handle_irq+0x27/0x40
[<ffffffff812e57de>] chv_gpio_irq_handler+0x7e/0x110
[<ffffffff810050aa>] handle_irq+0xaa/0x190
...
This is because desc->lock is raw_spinlock and is held when chv_gpio_irq_ack()
is called by the genirq core. chv_gpio_irq_ack() in turn takes pctrl->lock
which in -rt is an rt-mutex causing might_sleep() rightfully to complain about
sleeping function called from invalid context.
In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The Intel Baytrail pinctrl driver implements irqchip callbacks which are
called with desc->lock raw_spinlock held. In mainline this is fine because
spinlock resolves to raw_spinlock. However, running the same code in -rt we
get:
BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
Preemption disabled at:[<ffffffff81092e9f>] cpu_startup_entry+0x17f/0x480
CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #13
...
Call Trace:
<IRQ> [<ffffffff816283c6>] dump_stack+0x4a/0x61
[<ffffffff81077e17>] ___might_sleep+0xe7/0x170
[<ffffffff8162d6cf>] rt_spin_lock+0x1f/0x50
[<ffffffff812e3b88>] byt_gpio_clear_triggering+0x38/0x60
[<ffffffff812e3bc1>] byt_irq_mask+0x11/0x20
[<ffffffff810a7013>] handle_level_irq+0x83/0x150
[<ffffffff810a3457>] generic_handle_irq+0x27/0x40
[<ffffffff812e3a5f>] byt_gpio_irq_handler+0x7f/0xc0
[<ffffffff810050aa>] handle_irq+0xaa/0x190
...
This is because in -rt spinlocks are preemptible so taking the driver
private spinlock in irqchip callbacks causes might_sleep() to trigger.
In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.
Also shorten the critical section a bit in few places.
Suggested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
platform_driver does not need to set an owner as it will be
populated by the driver core.
The semantic patch that makes this change is available
in scripts/coccinelle/api/platform_no_drv_owner.cocci.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Group names should be smc0_nand_grp and smc0_nor_grp, otherwise you'll
get errors like this if you try to pinmux them via the devicetree:
zynq-pinctrl 700.pinctrl: invalid group "smc0_nand_grp" for function "smc0_nand"
Probably a typo while creating these tables.
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Moritz Fischer <moritz.fischer@ettus.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pfc in the R8A7790 (and probably others in the R-Car gen 2 family)
supports switching SDHI signals between 3.3V and 1.8V nominal voltage,
and the SD driver should do that when switching to and from UHS modes.
Add a flag for pins that have configurable I/O voltage and SoC
operations to get and set the nominal voltage. Implement the pinconf
power-source parameter using these operations.
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
If the gpio DT node has the gpio-ranges property, the range will be
added by the gpio core and doesn't need to be added by the pinctrl
driver.
By having the gpio-ranges property, we have an explicit dependency from
the gpio node to the pinctrl node and we can stop using the deprecated
pinctrl_add_gpio_range() function.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
To set/get atlas7 pull & drive strength, we use lots of if/else
to check pad type. But except mask value or immediate value, all
actions in these conditional branches are the same.
So we use predefined pull info table and drive strength table
to reduce these redundancy code.
Signed-off-by: Wei Chen <Wei.Chen@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
There is a hardware issue in Intel Baytrail where concurrent GPIO register
access might result reads of 0xffffffff and writes might get dropped
completely.
Prevent this from happening by taking the serializing lock in all places
where it is possible that more than one thread might be accessing the
hardware concurrently.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The FSF address is already mentioned in the COPYING file. No need to
duplicate that information to individual files.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
