Imran Shaik
3e86e57356
dt-bindings: clock: qcom: Add QCS8300 video clock controller
...
The QCS8300 video clock controller is a derivative of SA8775P, but
QCS8300 has minor difference. Hence, reuse the SA8775P videocc bindings
for QCS8300 platform.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com >
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-5-63e8ac268b02@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org >
2025-02-02 20:59:04 -06:00
Imran Shaik
0e193cc558
dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300
...
The QCS8300 camera clock controller is a derivative of SA8775P, but has
an additional clock and minor differences. Hence, reuse the SA8775P
camera bindings and add additional clock required for QCS8300.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com >
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-3-63e8ac268b02@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org >
2025-02-02 20:59:04 -06:00
Imran Shaik
f0ada00a9b
dt-bindings: clock: qcom: Add GPU clocks for QCS8300
...
The QCS8300 GPU clock controller is a derivative of SA8775P, but has few
additional clocks and minor differences. Hence, reuse gpucc bindings of
SA8775P and add additional clocks required for QCS8300.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com >
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-1-63e8ac268b02@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org >
2025-02-02 20:59:04 -06:00
Stephen Boyd
1d2da923fb
Merge branches 'clk-airoha', 'clk-rockchip', 'clk-stm', 'clk-thead' and 'clk-bcm' into clk-next
...
* clk-airoha:
clk: en7523: Add clock for eMMC for EN7581
dt-bindings: clock: add ID for eMMC for EN7581
dt-bindings: clock: drop NUM_CLOCKS define for EN7581
clk: en7523: Rework clock handling for different clock numbers
clk: en7523: Initialize num before accessing hws in en7523_register_clocks()
clk: en7523: Fix wrong BUS clock for EN7581
clk: amlogic: axg-audio: revert reset implementation
Revert "clk: Fix invalid execution of clk_set_rate"
* clk-rockchip:
clk: rockchip: rk3588: make refclko25m_ethX critical
clk: rockchip: rk3588: drop RK3588_LINKED_CLK
clk: rockchip: implement linked gate clock support
clk: rockchip: expose rockchip_clk_set_lookup
clk: rockchip: rk3588: register GATE_LINK later
clk: rockchip: support clocks registered late
* clk-stm:
clk: stm32f4: support spread spectrum clock generation
clk: stm32f4: use FIELD helpers to access the PLLCFGR fields
dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking
dt-bindings: clock: convert stm32 rcc bindings to json-schema
* clk-thead:
clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks
clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot
clk: thead: Fix clk gate registration to pass flags
* clk-bcm:
clk: bcm: rpi: Add disp clock
clk: bcm: rpi: Create helper to retrieve private data
clk: bcm: rpi: Enable minimize for all firmware clocks
clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks
clk: bcm: rpi: Add ISP to exported clocks
2025-01-21 11:22:26 -08:00
Stephen Boyd
b2fee97e6f
Merge branches 'clk-microchip', 'clk-xilinx', 'clk-allwinner', 'clk-imx' and 'clk-qcom' into clk-next
...
* clk-microchip:
clk: at91: sama7d65: add sama7d65 pmc driver
dt-bindings: clock: Add SAMA7D65 PMC compatible string
dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65
clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks
dt-bindings: clk: at91: Add clock IDs for the slow clock controller
* clk-xilinx:
clk: clocking-wizard: calculate dividers fractional parts
dt-bindings: clock: xilinx: Add reset GPIO for VCU
dt-bindings: clock: xilinx: Convert VCU bindings to dtschema
* clk-allwinner:
clk: sunxi-ng: h616: Reparent CPU clock during frequency changes
clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent
clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI
dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI
* clk-imx:
clk: imx: Apply some clks only for i.MX93
arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock
clk: imx93: Add IMX93_CLK_SPDIF_IPG clock
dt-bindings: clock: imx93: Add SPDIF IPG clk
clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x
clk: imx8mp: Fix clkout1/2 support
* clk-qcom: (63 commits)
clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC
dt-bindings: clock: move qcom,x1e80100-camcc to its own file
clk: qcom: smd-rpm: Add clocks for MSM8940
dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible
clk: qcom: smd-rpm: Add clocks for MSM8937
dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible
clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks
dt-bindings: interconnect: Add Qualcomm IPQ5424 support
clk: qcom: Add SM6115 LPASSCC
dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs
clk: qcom: gcc-sdm845: Add general purpose clock ops
clk: qcom: clk-rcg2: split __clk_rcg2_configure function
clk: qcom: clk-rcg2: document calc_rate function
clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC
clk: qcom: ipq5424: add gcc_xo_clk
dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro
dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro
clk: qcom: ipq5424: remove apss_dbg clock
dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible
...
2025-01-21 11:22:19 -08:00
Stephen Boyd
70741cc384
Merge branches 'clk-cleanup', 'clk-renesas', 'clk-mediatek', 'clk-samsung' and 'clk-socfpga' into clk-next
...
- Support for 5L35023 variant of Versa 3 clock generator
* clk-cleanup:
clk: analogbits: Fix incorrect calculation of vco rate delta
clk: Use str_enable_disable-like helpers
clk: clk-loongson2: Switch to use devm_clk_hw_register_fixed_rate_parent_data()
clk: starfive: Make _clk_get become a common helper function
clk: ep93xx: make const read-only arrays static
clk: lmk04832: make read-only const arrays static
clk: ti: use kcalloc() instead of kzalloc()
dt-bindings: clock: st,stm32mp1-rcc: complete the reference path
dt-bindings: clock: st,stm32mp1-rcc: fix reference paths
dt-bindings: clock: ti: Convert composite.txt to json-schema
dt-bindings: clock: ti: Convert gate.txt to json-schema
clk: Drop obsolete devm_clk_bulk_get_all_enable() helper
PCI: exynos: Switch to devm_clk_bulk_get_all_enabled()
soc: mediatek: pwrap: Switch to devm_clk_bulk_get_all_enabled()
clk: davinci: remove platform data struct
clk: fix an OF node reference leak in of_clk_get_parent_name()
clk: mmp: pxa1908-apbc: Fix NULL vs IS_ERR() check
clk: mmp: pxa1908-apbcp: Fix a NULL vs IS_ERR() check
clk: mmp: pxa1908-mpmu: Fix a NULL vs IS_ERR() check
* clk-renesas: (24 commits)
dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
clk: renesas: r9a09g057: Add clock and reset entries for GIC
clk: renesas: r9a09g057: Add reset entry for SYS
clk: renesas: r8a779g0: Add VSPX clocks
clk: renesas: r8a779g0: Add FCPVX clocks
clk: renesas: r9a09g047: Add I2C clocks/resets
clk: renesas: r9a09g047: Add CA55 core clocks
clk: renesas: rzv2h: Add support for RZ/G3E SoC
clk: renesas: rzv2h: Add MSTOP support
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
clk: versaclock3: Add support for the 5L35023 variant
dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator
clk: versaclock3: Prepare for the addition of 5L35023 device
clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP
clk: renesas: r8a779h0: Add display clocks
clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets
clk: renesas: rzv2h: Add selective Runtime PM support for clocks
clk: renesas: r9a06g032: Use BIT macro consistently
...
* clk-mediatek:
clk: ralink: mtmips: remove duplicated 'xtal' clock for Ralink SoC RT3883
clk: mediatek: mt2701-img: add missing dummy clk
clk: mediatek: mt2701-mm: add missing dummy clk
clk: mediatek: mt2701-bdp: add missing dummy clk
clk: mediatek: mt2701-aud: fix conversion to mtk_clk_simple_probe
clk: mediatek: mt2701-vdec: fix conversion to mtk_clk_simple_probe
* clk-samsung:
clk: samsung: Introduce Exynos990 clock controller driver
clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x}
dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings
* clk-socfpga:
clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
2025-01-21 11:22:03 -08:00
Dario Binacchi
223d32eb10
dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking
...
The addition of DT bindings for enabling and tuning spread spectrum
clocking generation is available only for the main PLL of stm32f{4,7}
platforms.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20250114182021.670435-3-dario.binacchi@amarulasolutions.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-15 15:17:05 -08:00
Dario Binacchi
ebca39700f
dt-bindings: clock: convert stm32 rcc bindings to json-schema
...
The patch converts st,stm32-rcc.txt to the JSON schema, but it does more
than that. The old bindings, in fact, only covered the stm32f{4,7}
platforms and not the stm32h7. Therefore, to avoid patch submission tests
failing, it was necessary to add the corresponding compatible (i. e.
st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead
of the 2 required for the stm32f{4,7} platforms.
Additionally, the old bindings made no mention of the st,syscfg property,
which is used by both the stm32f{4,7} and the stm32h7 platforms.
The patch also fixes the files referencing to the old st,stm32-rcc.txt.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20250114182021.670435-2-dario.binacchi@amarulasolutions.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-15 15:17:05 -08:00
Bryan O'Donoghue
7ec95ff9ab
dt-bindings: clock: move qcom,x1e80100-camcc to its own file
...
Add an x1e80100 camcc binding. x1e80100 has two power-domain parents unlike
other similar camcc controllers.
Differentiate the new structure into a unique camcc definition. Other
similar camcc controller setups can then be easily added to this one.
Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org >
Link: https://lore.kernel.org/r/20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-2-cb66d55d20cc@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-07 21:06:57 -06:00
Daniil Titov
ec2514d537
dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible
...
Document the qcom,rpmcc-msm8940 compatible.
Signed-off-by: Daniil Titov <daniilt971@gmail.com >
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org >
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org >
Link: https://lore.kernel.org/r/20241231-rpmcc-v1-3-1212df9b2042@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-07 21:06:13 -06:00
Daniil Titov
40106d4fac
dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible
...
Document the qcom,rpmcc-msm8937 compatible.
Signed-off-by: Daniil Titov <daniilt971@gmail.com >
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org >
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org >
Link: https://lore.kernel.org/r/20241231-rpmcc-v1-1-1212df9b2042@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-07 21:06:12 -06:00
Konrad Dybcio
030de8eafd
dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
...
SM6115 (and its derivatives or similar SoCs) has an LPASS clock
controller block which provides audio-related resets.
Add bindings for it.
Cc: Konrad Dybcio <konradybcio@kernel.org >
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com >
Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org >
[alexey.klimov slightly changed the commit message]
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org >
Link: https://lore.kernel.org/r/20241212002551.2902954-2-alexey.klimov@linaro.org
[bjorn: Adjusted Konrad's address]
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-07 20:29:27 -06:00
Rohit Visavalia
b00b08a596
dt-bindings: clock: xilinx: Add reset GPIO for VCU
...
It is marked as optional as some of the ZynqMP designs are having vcu_reset
(reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another
PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
axi_gpio or PS GPIO so there will be no GPIO entry.
Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com >
Link: https://lore.kernel.org/r/20250107044038.100945-3-rohit.visavalia@amd.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-07 11:48:23 -08:00
Rohit Visavalia
b51adc7755
dt-bindings: clock: xilinx: Convert VCU bindings to dtschema
...
Convert AMD (Xilinx) VCU bindings to yaml format.
Additional changes:
- move xlnx_vcu DT binding to clock from soc following commit
a2fe7baa27rohit.visavalia@xilinx.com >
Link: https://lore.kernel.org/r/20250107044038.100945-2-rohit.visavalia@amd.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-07 11:48:14 -08:00
Stephen Boyd
83f6c3dea9
Merge tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
...
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the RZ/G3E (R9A09G047) SoC
- Add Module Stop (MSTOP) support on RZ/V2H
- Add Image Signal Processor helper block (FCPVX and VSPX) clocks on
R-Car V4H SoC
- Add System Controller (SYS) reset and Generic Interrupt Controller
(GIC) clock and reset entries on RZ/V2H
* tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
clk: renesas: r9a09g057: Add clock and reset entries for GIC
clk: renesas: r9a09g057: Add reset entry for SYS
clk: renesas: r8a779g0: Add VSPX clocks
clk: renesas: r8a779g0: Add FCPVX clocks
clk: renesas: r9a09g047: Add I2C clocks/resets
clk: renesas: r9a09g047: Add CA55 core clocks
clk: renesas: rzv2h: Add support for RZ/G3E SoC
clk: renesas: rzv2h: Add MSTOP support
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
2025-01-07 11:42:23 -08:00
Richard Acayan
bf6aa2d693
dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible
...
The camera clocks on SDM670 and SDM845 have no significant differences
that would require a change in the clock controller driver. The only
difference is the clock frequency at each level of the power domains,
which is not specified in the clock driver. There should still be a
compatible specific to the SoC, so add the compatible for SDM670 with
the SDM845 compatible as fallback.
Link: d4dc50c0a9/drivers/clk/qcom/camcc-sdm845.c (2048)vladimir.zapolskiy@linaro.org >
Suggested-by: Konrad Dybcio <konradybcio@kernel.org >
Link: https://lore.kernel.org/linux-arm-msm/7d26a62b-b898-4737-bd53-f49821e3b471@linaro.org
Signed-off-by: Richard Acayan <mailingradian@gmail.com >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20241218231729.270137-8-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 18:10:53 -06:00
Dmitry Baryshkov
2b5add606c
dt-bindings: clock: qcom,mmcc: support LVDS PLL input for apq8064
...
APQ8064 / MSM8960 have separate LVDS PLL driving the LVDS / LCDC clock.
Add corresponding input to clock controller bindings.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-1-c95d2e2bf143@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 18:05:27 -06:00
Dario Binacchi
caa508a38e
dt-bindings: clock: st,stm32mp1-rcc: complete the reference path
...
All other paths referenced in the file follow a scheme starting from the
Linux root. The patch adjusts the single file that deviated from this
scheme, making it consistent with the others.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com >
Link: https://lore.kernel.org/r/20241231150144.4035938-2-dario.binacchi@amarulasolutions.com
Acked-by: Krzysztof Kozlowski <krzk@kernel.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-06 15:48:05 -08:00
Dario Binacchi
c5dcc2804d
dt-bindings: clock: st,stm32mp1-rcc: fix reference paths
...
The path of the two files was wrong even at the time they were added.
Let's fix them so they can be correctly referenced.
Fixes: 722dc8a1d520107d7328dario.binacchi@amarulasolutions.com >
Link: https://lore.kernel.org/r/20241231150144.4035938-1-dario.binacchi@amarulasolutions.com
Acked-by: Krzysztof Kozlowski <krzk@kernel.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-06 15:48:01 -08:00
Andreas Kemnade
dc39d7fa60
dt-bindings: clock: ti: Convert composite.txt to json-schema
...
Convert the OMAP gate clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
Choose GPL-only license because original binding was also GPL.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info >
Link: https://lore.kernel.org/r/20250105170854.408875-3-andreas@kemnade.info
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-06 15:45:34 -08:00
Andreas Kemnade
be7638a0d5
dt-bindings: clock: ti: Convert gate.txt to json-schema
...
Convert the OMAP gate clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
Choose GPL-only license because original binding was also GPL.
Clean up the examples during conversion to meet modern standards and
remove examples with no additional value.
Due to usage in code and existing devicetree binding, add the
ti,set-rate-parent property.
Signed-off-by: Andreas Kemnade <andreas@kemnade.info >
Link: https://lore.kernel.org/r/20250105170854.408875-2-andreas@kemnade.info
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2025-01-06 15:45:11 -08:00
Bjorn Andersson
62ede76a7b
Merge branch '20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com' into clk-for-6.14
...
Merge the IPQ CMN PLL clock binding through a topic branch to make it
available to DeviceTree source branches as well.
2025-01-06 17:41:49 -06:00
Luo Jie
c0f1cbf795
dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC
...
The CMN PLL controller provides clocks to networking hardware blocks
and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
on-chip Wi-Fi, and produces output clocks at fixed rates. These output
rates are predetermined, and are unrelated to the input clock rate.
The primary purpose of CMN PLL is to supply clocks to the networking
hardware such as PPE (packet process engine), PCS and the externally
connected switch or PHY device. The CMN PLL block also outputs fixed
rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
clock supplied to GCC.
Signed-off-by: Luo Jie <quic_luoj@quicinc.com >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 17:41:39 -06:00
Bjorn Andersson
9d46289f18
Merge branch '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into clk-for-6.14
...
Merge SM8750 display clock controller bindings through topic branch, to
make available to DeviceTree source branch as well.
2025-01-06 10:30:24 -06:00
Krzysztof Kozlowski
4f1a62e2b3
dt-bindings: clock: qcom,sm8550-dispcc: Add SM8750 DISPCC
...
Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC).
Bindings are similar to existing SM8550 and SM8650 (same clock inputs),
but the clock hierarchy is quite different and these are not compatible
devices.
The binding header was copied from downstream sources, so I retained
original copyrights.
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 10:30:00 -06:00
Taniya Das
6badb455ae
dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for SM8750
...
Update the documentation for clock rpmh driver on SM8750 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Taniya Das <quic_tdas@quicinc.com >
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-1-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 10:28:32 -06:00
Bjorn Andersson
4188e51685
Merge branch '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' into clk-for-6.14
...
Merge the SM8750 GCC and TCSR clock bindings through topic branch, to
allow merging into DeviceTree source branch as well.
2025-01-06 10:27:11 -06:00
Taniya Das
8817c21a45
dt-bindings: clock: qcom: Document the SM8750 TCSR Clock Controller
...
Add bindings documentation for the SM8750 Clock Controller.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com >
Signed-off-by: Taniya Das <quic_tdas@quicinc.com >
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-7-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 10:27:00 -06:00
Taniya Das
42b00f4456
dt-bindings: clock: qcom: Add SM8750 GCC
...
Add device tree bindings for the global clock controller on Qualcomm
SM8750 platform.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com >
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com >
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-5-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2025-01-06 10:27:00 -06:00
Taniya Das
9446506226
dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for QCS615
...
Add bindings and update documentation for clock rpmh driver on QCS615
SoCs.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Taniya Das <quic_tdas@quicinc.com >
Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-1-3d716ad0d987@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2024-12-25 22:53:22 -06:00
Konrad Dybcio
089c09ee12
dt-bindings: clock: qcom,x1e80100-gcc: Add X1P42100
...
X1P42100 is based on X1E80100 and largely reuses the X1E80100's GCC
block, adding a couple wires here and there.
Add a compatible for the X1P4 with a fallback to X1E80100. There are
some additions in the smaller one, that will be added in the future.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com >
Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-1-dbaeccb74884@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2024-12-25 21:57:36 -06:00
Bjorn Andersson
75c5cb35a8
Merge branch '20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com' into clk-for-6.14
...
Merge the X1P42100 GPUCC binding through a topic branch to make
available for the DeviceTree branch as well.
2024-12-25 21:56:50 -06:00
Konrad Dybcio
e8f81b5613
dt-bindings: clock: qcom,x1e80100-gpucc: Extend for X1P42100
...
To make it easier for X1P4 and X1E to share a common device tree base,
extend the existing latter's GPUCC bindings and reuse them on the
former platform.
While not in the same file, it only makes sense to introduce the new
compatible in this commit as well.
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com >
Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2024-12-25 21:56:30 -06:00
Dharma Balasubiramani
1c9eb9e684
dt-bindings: clock: Add SAMA7D65 PMC compatible string
...
Add the `microchip,sama7d65-pmc` compatible string to the existing binding,
since the SAMA7D65 PMC shares the same properties and clock requirements
as the SAMA7G5.
Export MCK3 and MCK5 to be accessed and referenced in DT to assign to
the clocks property for sama7d65 SoC.
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com >
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com >
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev >
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Link: https://lore.kernel.org/r/5252a28531deaee67af1edd8e72d45ca57783464.1733505542.git.Ryan.Wanner@microchip.com
[claudiu.beznea: use tabs instead of spaces in
include/dt-bindings/clock/at91.h]
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev >
2024-12-17 10:10:21 +02:00
Dharma Balasubiramani
188002bd23
dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65
...
Add bindings for SAMA7D65's slow clock controller.
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com >
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com >
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev >
Link: https://lore.kernel.org/r/b7a8a22a571f6fc2be56a25f26757f37fa8d2bb3.1733505542.git.Ryan.Wanner@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev >
2024-12-17 10:10:20 +02:00
Igor Belwon
5feae3e79d
dt-bindings: clock: samsung: Add Exynos990 SoC CMU bindings
...
Add dt-schema documentation for the Exynos990 SoC CMU.
This clock management unit has a topmost block (CMU_TOP)
that generates top clocks for other blocks. Currently the
only other block implemented is CMU_HSI0, which provides
clocks for the USB part of the SoC.
Also, device-tree binding definitions added for these blocks:
- CMU_TOP
- CMU_HSI0
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org >
Link: https://lore.kernel.org/r/20241209-exynos990-cmu-v4-1-57f07080f9e4@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
2024-12-14 11:38:54 +01:00
Biju Das
25458fdd39
dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
...
Document the device tree bindings for the Renesas RZ/G3E SoC
Clock Pulse Generator (CPG).
Also define constants for the core clocks of the RZ/G3E SoC.
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be >
Link: https://lore.kernel.org/20241203105005.103927-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be >
2024-12-13 11:02:26 +01:00
Krzysztof Kozlowski
9d40c5a698
dt-bindings: clock: qcom,sc7280-lpasscorecc: add top-level constraints
...
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for reg, clocks and clock-names.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Acked-by: Rob Herring (Arm) <robh@kernel.org >
Link: https://lore.kernel.org/r/20240817094605.27185-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2024-12-11 21:56:33 -06:00
Krzysztof Kozlowski
2a5711c7dc
dt-bindings: clock: qcom,sc7280-lpasscorecc: order properties to match convention
...
By convention we expect first "compatible", then "reg" and then rest.
Order properties to match convention and what is in "required:" block.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Acked-by: Rob Herring (Arm) <robh@kernel.org >
Link: https://lore.kernel.org/r/20240817094605.27185-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2024-12-11 21:56:33 -06:00
Claudiu Beznea
626b77735a
dt-bindings: clock: versaclock3: Document 5L35023 Versa3 clock generator
...
There are some differences b/w 5L35023 and 5P35023 Versa3 clock
generator variants but the same driver could be used with minimal
adjustments. The identified differences are PLL2 Fvco, the clock sel
bit for SE2 clock and different default values for some registers.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com >
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be >
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com >
Link: https://lore.kernel.org/r/20241210170953.2936724-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-12-10 14:49:27 -08:00
Taniya Das
f4d3d7340e
dt-bindings: clock: qcom: Add QCS615 GCC clocks
...
Add device tree bindings for global clock controller on QCS615 SoCs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org >
Signed-off-by: Taniya Das <quic_tdas@quicinc.com >
Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-3-3d716ad0d987@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2024-12-01 22:04:24 -06:00
Stephen Boyd
21a5352dc7
Merge branches 'clk-marvell', 'clk-adi', 'clk-qcom' and 'clk-devm' into clk-next
...
- Add devm_clk_bulk_get_all_enabled() to return number of clks acquired
- Marvell PXA1908 SoC clks
* clk-marvell:
clk: mmp: Add Marvell PXA1908 MPMU driver
clk: mmp: Add Marvell PXA1908 APMU driver
clk: mmp: Add Marvell PXA1908 APBCP driver
clk: mmp: Add Marvell PXA1908 APBC driver
dt-bindings: clock: Add Marvell PXA1908 clock bindings
clk: mmp: Switch to use struct u32_fract instead of custom one
* clk-adi:
clk: clk-axi-clkgen: make sure to enable the AXI bus clock
dt-bindings: clock: axi-clkgen: include AXI clk
* clk-qcom: (43 commits)
clk: qcom: remove unused data from gcc-ipq5424.c
clk: qcom: Add support for Global Clock Controller on QCS8300
dt-bindings: clock: qcom: Add GCC clocks for QCS8300
clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC
clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding
clk: qcom: add SAR2130P GPU Clock Controller support
clk: qcom: dispcc-sm8550: enable support for SAR2130P
clk: qcom: tcsrcc-sm8550: add SAR2130P support
clk: qcom: add support for GCC on SAR2130P
clk: qcom: rpmh: add support for SAR2130P
clk: qcom: rcg2: add clk_rcg2_shared_floor_ops
dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles
dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible
dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible
dt-bindings: clock: qcom: document SAR2130P Global Clock Controller
dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible
clk: qcom: Make GCC_6125 depend on QCOM_GDSC
dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros
dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros
...
* clk-devm:
clk: Provide devm_clk_bulk_get_all_enabled() helper
2024-11-18 20:01:35 -08:00
Stephen Boyd
0cf32b1f37
Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and 'clk-allwinner' into clk-next
...
* clk-samsung:
clk: samsung: Introduce Exynos8895 clock driver
clk: samsung: clk-pll: Add support for pll_{1051x,1052x}
dt-bindings: clock: samsung: Add Exynos8895 SoC
clk: samsung: gs101: make all ufs related clocks critical
clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support
dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
clk: samsung: Fix out-of-bound access of of_match_node()
dt-bindings: clock: samsung: remove define with number of clocks for FSD
clk: samsung: fsd: do not define number of clocks in bindings
clk: samsung: Fix errors reported by checkpatch
clk: samsung: Fix block comment style warnings reported by checkpatch
* clk-microchip:
clk: lan966x: add support for lan969x SoC clock driver
clk: lan966x: prepare driver for lan969x support
clk: lan966x: make clk_names const char * const
dt-bindings: clock: add support for lan969x
* clk-imx:
clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains()
clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restore
clk: imx: clk-scu: fix clk enable state save and restore
clk: imx: fracn-gppll: fix pll power up
clk: imx: fracn-gppll: correct PLL initialization flow
clk: imx: lpcg-scu: SW workaround for errata (e10858)
clk: imx: add i.MX91 clk
dt-bindings: clock: Add i.MX91 clock support
dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition
clk: imx93: Move IMX93_CLK_END macro to clk driver
clk: imx95-blk-ctl: Add one clock gate for HSIO block
dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL
* clk-amlogic:
clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX
clk: amlogic: axg-audio: use the auxiliary reset driver
reset: amlogic: Fix small whitespace issue
reset: amlogic: add auxiliary reset driver support
reset: amlogic: split the device core and platform probe
reset: amlogic: move drivers to a dedicated directory
reset: amlogic: add reset status support
reset: amlogic: use reset number instead of register count
reset: amlogic: add driver parameters
reset: amlogic: make parameters unsigned
reset: amlogic: use generic data matching function
reset: amlogic: convert driver to regmap
dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema
clk: meson: meson8b: remove spinlock
clk: meson: mpll: Delete a useless spinlock from the MPLL
clk: meson: s4: pll: fix frac maximum value for hifi_pll
clk: meson: c3: pll: fix frac maximum value for hifi_pll
clk: meson: Support PLL with fixed fractional denominators
clk: meson: s4: pll: hifi_pll support fractional multiplier
* clk-allwinner:
clk: sunxi-ng: Use of_property_present() for non-boolean properties
clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
clk: sunxi-ng: Constify struct ccu_reset_map
clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
2024-11-18 20:01:28 -08:00
Stephen Boyd
b2f8240153
Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and 'clk-bindings' into clk-next
...
- Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver
- TWL6030 clk driver
- Nuvoton Arbel BMC NPCM8XX SoC clks
- Convert more clk bindings to YAML
* clk-mobileye:
clk: eyeq: add EyeQ6H west fixed factor clocks
clk: eyeq: add EyeQ6H central fixed factor clocks
clk: eyeq: add EyeQ5 fixed factor clocks
clk: eyeq: add fixed factor clocks infrastructure
clk: eyeq: require clock index with phandle in all cases
clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
clk: eyeq: add driver
clk: divider: Introduce CLK_DIVIDER_EVEN_INTEGERS flag
dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes
Revert "dt-bindings: clock: mobileye,eyeq5-clk: add bindings"
* clk-twl:
clk: twl: add TWL6030 support
clk: twl: remove is_prepared
* clk-nuvoton:
clk: npcm8xx: add clock controller
reset: npcm: register npcm8xx clock auxiliary bus device
dt-bindings: reset: npcm: add clock properties
* clk-renesas:
clk: renesas: vbattb: Add VBATTB clock driver
clk: Add devm_clk_hw_register_gate_parent_hw()
clk: renesas: rzg2l: Fix FOUTPOSTDIV clk
dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
clk: renesas: r9a08g045: Add power domain for RTC
clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe
clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones
clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup()
dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks
clk: renesas: r9a09g057: Add clock and reset entries for ICU
clk: renesas: r9a09g057: Add CA55 core clocks
clk: renesas: Remove duplicate and trailing empty lines
* clk-bindings:
dt-bindings: clock: actions,owl-cmu: convert to YAML
dt-bindings: clock: ti: Convert mux.txt to json-schema
dt-bindings: clock: ti: Convert divider.txt to json-schema
dt-bindings: clock: ti: Convert interface.txt to json-schema
dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML
2024-11-18 20:00:28 -08:00
Stephen Boyd
6af88ccfcb
Merge branches 'clk-cleanup', 'clk-mediatek', 'clk-kunit', 'clk-xilinx' and 'clk-fixed-gate' into clk-next
...
- Various clk driver cleanups
- MediaTek MT6735 SoC clks
- MediaTek MT7620, MT7628 and MT7688 MMC clks
- KUnit tests for clk-assigned-rates{,-u64}
- Add a driver for gated fixed rate clocks
* clk-cleanup:
clk: clk-loongson2: Fix potential buffer overflow in flexible-array member access
clk: Fix invalid execution of clk_set_rate
clk: clk-loongson2: Fix memory corruption bug in struct loongson2_clk_provider
clk: lan966x: make it selectable for ARCH_LAN969X
clk: clk-apple-nco: Add NULL check in applnco_probe
clk: starfive: jh7110-pll: Mark the probe function as __init
clk: sophgo: avoid integer overflow in sg2042_pll_recalc_rate()
clk: tegra: use clamp() in tegra_bpmp_clk_determine_rate()
clk: cdce925: make regmap_cdce925_bus constant
clk: Drop explicit initialization of struct i2c_device_id::driver_data to 0
clk: clk-qoriq: Replace of_node_put() with __free()
clk: Remove unused clk_hw_rate_is_protected
* clk-mediatek:
clk: en7523: map io region in a single block
clk: en7523: move en7581_reset_register() in en7581_clk_hw_init()
clk: en7523: fix estimation of fixed rate for EN7581
clk: en7523: introduce chip_scu regmap
clk: en7523: move clock_register in hw_init callback
clk: en7523: remove REG_PCIE*_{MEM,MEM_MASK} configuration
dt-bindings: clock: airoha: Update reg mapping for EN7581 SoC.
clk: mediatek: Add drivers for MT6735 syscon clock and reset controllers
dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers
clk: mediatek: mt6735-apmixedsys: Fix an error handling path in clk_mt6735_apmixed_probe()
clk: ralink: mtmips: add mmc related clocks for SoCs MT7620, MT7628 and MT7688
clk: ralink: mtmips: fix clocks probe order in oldest ralink SoCs
clk: ralink: mtmips: fix clock plan for Ralink SoC RT3883
clk: mediatek: clk-mt8188-topckgen: Remove univpll from parents of mfg_core_tmp
clk: mediatek: Add drivers for MediaTek MT6735 main clock and reset drivers
dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings
clk: mediatek: drop two dead config options
* clk-kunit:
clk: Allow kunit tests to run without OF_OVERLAY enabled
clk: test: Add KUnit tests for clock-assigned-rates{-u64} DT properties
of: kunit: Extract some overlay boiler plate into macros
clk: test: Add test managed of_clk_add_hw_provider()
* clk-xilinx:
clk: clocking-wizard: move dynamic reconfig setup behind flag
dt-bindings: clock: xilinx: describe whether dynamic reconfig is enabled
clk: clocking-wizard: move clock registration to separate function
clk: clocking-wizard: use devres versions of clk_hw API
clk: clocking-wizard: use newer clk_hw API
clk: clocking-wizard: simplify probe/remove with devres helpers
* clk-fixed-gate:
clk: clk-gpio: add driver for gated-fixed-clocks
clk: clk-gpio: use dev_err_probe for gpio-get failure
clk: clk-gpio: update documentation for gpio-gate clock
dt-bindings: clocks: add binding for gated-fixed-clocks
2024-11-18 20:00:03 -08:00
Nuno Sa
47f3f5a82a
dt-bindings: clock: axi-clkgen: include AXI clk
...
In order to access the registers of the HW, we need to make sure that
the AXI bus clock is enabled. Hence let's increase the number of clocks
by one and add clock-names to differentiate between parent clocks and
the bus clock.
Fixes: 0e646c52cfnuno.sa@analog.com >
Link: https://lore.kernel.org/r/20241029-axi-clkgen-fix-axiclk-v2-1-bc5e0733ad76@analog.com
Reviewed-by: Conor Dooley <conor.dooley@microchip.com >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-11-14 14:43:40 -08:00
Stephen Boyd
53454b7a41
Merge tag 'v6.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-bindings
...
Pull a YAML conversion of the rk3328 clock controller binding from Heiko
Stuebner.
* tag 'v6.13-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML
2024-11-14 14:41:18 -08:00
Duje Mihanović
f03b086624
dt-bindings: clock: Add Marvell PXA1908 clock bindings
...
Add dt bindings and documentation for the Marvell PXA1908 clock
controller.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com >
Reviewed-by: Stephen Boyd <sboyd@kernel.org >
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr >
Link: https://lore.kernel.org/r/20241104-pxa1908-lkml-v13-4-e050609b8d6c@skole.hr
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-11-14 14:32:56 -08:00
Lorenzo Bianconi
0f7c637d11
dt-bindings: clock: airoha: Update reg mapping for EN7581 SoC.
...
clk-en7523 driver for EN7581 SoC is mapping all the scu memory region
while it is configuring the chip-scu one via a syscon. Update the reg
mapping definition for this device. This patch does not introduce any
backward incompatibility since the dts for EN7581 SoC is not upstream
yet.
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org >
Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-1-8ada5e394ae4@kernel.org
Reviewed-by: Rob Herring (Arm) <robh@kernel.org >
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-11-14 12:58:56 -08:00
Yassine Oudjana
a7479860bb
dt-bindings: clock: mediatek: Add bindings for MT6735 syscon clock and reset controllers
...
Add device tree bindings for syscon clock and reset controllers (IMGSYS,
MFGCFG, VDECSYS and VENCSYS).
Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com >
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com >
Acked-by: Conor Dooley <conor.dooley@microchip.com >
Link: https://lore.kernel.org/r/20241106111402.200940-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org >
2024-11-14 12:52:14 -08:00
