Charlene Liu
de08e41930
drm/amd/display: update sr_exit latency for z8
...
This is based on real asic performance result.
Reviewed-by: Alvin Lee <alvin.lee2@amd.com >
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com >
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-10-07 14:12:14 -04:00
Daniel Miess
c60e20f13c
drm/amd/display: Change dram_clock_latency to 34us for dcn351
...
[Why]
Intermittent underflow observed when using 4k144 display on
dcn351
[How]
Update dram_clock_change_latency_us from 11.72us to 34us
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com >
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com >
Signed-off-by: Daniel Miess <daniel.miess@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-06-19 14:17:25 -04:00
Xiang Yang
af068dc28d
drm/amd/display: delete the redundant initialization in dcn3_51_soc
...
the dram_clock_change_latency_us in dcn3_51_soc is initialized twice, so
delete one of them.
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Xiang Yang <xiangyang3@huawei.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-04-09 22:19:52 -04:00
Aric Cyr
aece2094e3
drm/amd/display: Fix compiler warnings on high compiler warning levels
...
[why]
Enabling higher compiler warning levels results in many issues that can
be trivially resolved as well as some potentially critical issues.
[how]
Fix all compiler warnings found with various compilers and higher
warning levels. Primarily, potentially uninitialized variables and
unreachable code.
Reviewed-by: Leo Li <sunpeng.li@amd.com >
Acked-by: Roman Li <roman.li@amd.com >
Signed-off-by: Aric Cyr <aric.cyr@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-04-09 22:05:04 -04:00
Sung Joon Kim
be524af47a
drm/amd/display: Update dcn351 to latest dcn35 config
...
[why & how]
There were some fixes in dcn35 that need
to be ported over to dcn351 to prevent any
regression.
Signed-off-by: Sung Joon Kim <sungkim@amd.com >
Reviewed-by: Liu, Xi (Alex) <xiliu102@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-03-27 01:35:12 -04:00
Xi Liu
398a16e1f0
drm/amd/display: increase bb clock for DCN351
...
[Why and how]
Bounding box clocks for DCN351 should be increased as per request
Reviewed-by: Swapnil Patel <swapnil.patel@amd.com >
Acked-by: Wayne Lin <wayne.lin@amd.com >
Signed-off-by: Xi Liu <xi.liu@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-03-22 15:49:21 -04:00
Natanel Roizenman
414998f2a0
drm/amd/display: Increase Z8 watermark times.
...
Increase Z8 watermark times from 210->250us and 320->350us.
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com >
Acked-by: Wayne Lin <wayne.lin@amd.com >
Signed-off-by: Natanel Roizenman <natanel.roizenman@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-03-22 15:49:00 -04:00
Hamza Mahfooz
2728e9c7c8
drm/amd/display: add DC changes for DCN351
...
Add DC support for DCN 3.5.1.
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-03-04 15:59:08 -05:00
