Isabella Basso
240e6d25a0
drm/amd/display: fix function scopes
...
This turns previously global functions into static, thus removing
compile-time warnings such as:
warning: no previous prototype for 'get_highest_allowed_voltage_level'
[-Wmissing-prototypes]
742 | unsigned int get_highest_allowed_voltage_level(uint32_t chip_family, uint32_t hw_internal_rev, uint32_t pci_revision_id)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
warning: no previous prototype for 'rv1_vbios_smu_send_msg_with_param'
[-Wmissing-prototypes]
102 | int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsigned int param)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Changes since v1:
- As suggested by Rodrigo Siqueira:
1. Rewrite function signatures to make them more readable.
2. Get rid of unused functions in order to remove 'defined but not
used' warnings.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com >
Signed-off-by: Isabella Basso <isabbasso@riseup.net >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2021-12-13 16:34:26 -05:00
Jake Wang
bda2446257
drm/amd/display: Disable dpstreamclk, symclk32_se, and symclk32_le
...
[Why & How]
Disable dpstreamclk, symclk32_se, and symclk32_le when not in use.
Reviewed-by: Ariel Bernstein <eric.yang2@amd.com >
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com >
Signed-off-by: Jake Wang <haonan.wang2@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2021-10-19 17:20:02 -04:00
Jake Wang
e22ad7e338
drm/amd/display: Disable dsc root clock when not being used
...
[Why & How]
Disable root clock for dsc when not being used.
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com >
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com >
Signed-off-by: Jake Wang <haonan.wang2@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2021-10-19 17:19:24 -04:00
Hansen
3cf79bb772
drm/amd/display: Fix DP2 SE and LE SYMCLK selection for B0 PHY
...
Remap phyd32clk to PHYF and PHYG for B0, PHYC and PHYD are unused
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com >
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com >
Signed-off-by: Hansen <Hansen.Dsouza@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2021-10-19 17:18:59 -04:00
Jake Wang
7a28bee067
drm/amd/display: Disable dpp root clock when not being used
...
[Why & How]
Disable root clock for dpp when not being used.
Reviewed-by: Eric Yang <eric.yang2@amd.com >
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com >
Signed-off-by: Jake Wang <haonan.wang2@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2021-10-19 17:17:16 -04:00
Fangzhi Zuo
d76b12da98
drm/amd/display: Add DP 2.0 DCCG
...
HW Blocks:
+--------+ +-----+ +------+
| OPTC | | HDA | | HUBP |
+--------+ +-----+ +------+
| | |
| | |
HPO ====|==========|========|====
| | v |
| | +-----+ |
| | | APG | |
| | +-----+ |
| | | |
| v v v
| +---------------------+
| | HPO Stream Encoder |
| +---------------------+
| |
| v
| +--------------------+
| | HPO Link Encoder |
| +--------------------+
| |
v ===============|=============
v
+------------------+
| DIO Output Mux |
+------------------+
|
v
+-----+
| PHY |
+-----+
| PHYD32CLK[0]
v
+------+
| DCCG |
+------+
|
v
SYMCLK32
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com >
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2021-09-01 16:55:10 -04:00
Nicholas Kazlauskas
d8a2b4f3a9
drm/amd/display: Add DCN3.1 DCCG
...
Add programming of the DCCG (Display Controller Clock Generator) block:
HW Blocks:
+--------+
| DCCG |
+--------+
Acked-by: Huang Rui <ray.huang@amd.com >
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2021-06-04 16:03:26 -04:00
