Commit Graph

35 Commits

Author SHA1 Message Date
Evan Quan
92859e0d5c drm/amd/powerplay: allow slow switch only if NBPState enabled v2
Otherwise there may be potential SMU performance issues.

v2: fix commit description and coding style

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rex.zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:14:35 -05:00
Evan Quan
f132d56162 drm/amd/powerplay: correct the argument for PPSMC_MSG_SetUclkFastSwitch
The argument was set wrongly. Fast/slow switch was asked when there is
actually a slow/fast switch needed.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <rex.zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-24 15:14:25 -05:00
Evan Quan
1ce0688f3f drm/amd/powerplay: fixed uninitialized value
The 'result' is not initialized correctly. It causes the API
return an error code even on success.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-07-19 13:56:43 -05:00
Alex Deucher
ce7577a219 drm/amdgpu/pp: split out common smumgr smu9 code
Split out the shared smumgr code for vega10 and 12
so we don't have duplicate code for both.

Reviewed-by: Rex Zhu <rezhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-16 11:39:22 -05:00
Evan Quan
ed515ce274 drm/amd/powerplay: convert the sclk/mclk into Mhz for comparation
Convert the clocks into right Mhz unit. Otherwise, it will miss
the equal situation.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13 14:45:16 -05:00
Evan Quan
991a6b32ce drm/amd/powerplay: add vega12 SMU gfxoff support v3
Export apis for enabling/disabling SMU gfxoff support.

v2: fit the latest gfxoff support framework
v3: add feature_mask control

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-13 14:45:01 -05:00
Rex Zhu
ed0926647d drm/amd/pp: Convert 10KHz to KHz as variable name
The default clock unit in powerplay is 10KHz.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-10 14:16:53 -05:00
Rex Zhu
20582319bc drm/amd/pp: Remove the same struct define in powerplay
delete the same struct define in powerplay, share the struct
with display.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:02 -05:00
Rex Zhu
860c15e903 drm/amd/pp: Remove duplicate code in vega12_hwmgr.c
use smu_helper function smu_set_watermarks_for_clocks_ranges
in vega12_set_watermarks_for_clocks_ranges.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:57 -05:00
Rex Zhu
99c5e27d33 drm/amd/pp: Refine the interface exported to display
use void * as function parameter type in order for extension.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:57 -05:00
Rex Zhu
23ec3d1479 drm/amd/pp: Convert clock unit to KHz as defined
Convert clock unit 10KHz to KHz as the data sturct defined.
e.g.
struct pp_clock_with_latency {
	uint32_t clocks_in_khz;
	uint32_t latency_in_us;
};
Meanwhile revert the same conversion in display side.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:55 -05:00
Evan Quan
0c3d017445 drm/amd/powerplay: cosmetic fix
Fix coding style and drop unused variable.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:56 -05:00
Evan Quan
6ad87101f3 drm/amd/powerplay: correct vega12 thermal support as true
Thermal support is enabled on vega12.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:56 -05:00
Evan Quan
28a7b4f449 drm/amd/powerplay: set vega12 pre display configurations
Set num_displays to 0 and force uclk high as part of the mode
set sequence.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:56 -05:00
Evan Quan
e17c7f92b2 drm/amd/powerplay: apply clocks adjust rules on power state change
This add the apply_clocks_adjust_rules callback which is used
to validate the clock settings on a power state change.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:55 -05:00
Evan Quan
a0a59c8fc7 drm/amd/powerplay: correct vega12 max num of dpm level
Use MAX_NUM_CLOCKS instead of VG12_PSUEDO* macros for
the max number of dpm levels.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:55 -05:00
Evan Quan
3022256180 drm/amd/powerplay: drop unnecessary uclk hard min setting
We don't need to set uclk hard min here because this will
be set with other clocks on power state change.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:55 -05:00
Evan Quan
ac32b06ace drm/amd/powerplay: correct smc display config for multi monitor
Need to take into account multi-head with synced displays.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:54 -05:00
Evan Quan
f74aa69d0a drm/amd/powerplay: initialize uvd/vce powergate status v4
On UVD/VCE dpm enabled/disabled, the powergate status will be
set as false/true. So that we will not try to ungate/gate them(
enable/disable their dpm) again.

v2: added check for uvd/vce powergate status before gating
v3: fix typo in description
v4: warning fix (Alex)

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:54 -05:00
Evan Quan
8fd2636170 drm/amd/powerplay: revise clock level setup
Make sure the clock level set only on dpm enabled. Also uvd/vce/soc
clock also changed correspondingly.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:53 -05:00
Evan Quan
70fef5741c drm/amd/powerplay: retrieve all clock ranges on startup
So that we do not need to use PPSMC_MSG_GetMin/MaxDpmFreq to
get the clock ranges on runtime. Since that causes some problems.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:53 -05:00
Evan Quan
3b579c5483 drm/amd/powerplay: revise default dpm tables setup
Initialize the soft/hard min/max level correctly and
handle the dpm disabled situation.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:53 -05:00
Evan Quan
acee16f4de drm/amd/powerplay: correct vega12 bootup values settings
The vbios firmware structure changed between v3_1 and v3_2. So,
the code to setup bootup values needs different paths based
on header version.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:52 -05:00
Rex Zhu
5b79d0482f drm/amd/pp: Remove struct pp_gpu_power
Currently smu only calculate average gpu power in real time.

for vddc/vddci/max power,
User need to set start time and end time, firmware can calculate
the average vddc/vddci/max power. but the type of return values
is not unified. For Vi, return type is uint.
For vega, return type is float.

so this struct can't be suitable for all asics.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:43:18 -05:00
Kenneth Feng
0bc8f3d29b drm/amd/powerplay: initialzie the dpm intial enabled state
To expose the right dpm levels to the sysfs

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:43:09 -05:00
Kenneth Feng
61279073b1 amd/powerplay: implement the vega12_force_clock_level interface
pp_dpm_sclk/pp_dpm_mclk in sysfs implemented to force
gfxclk/uclk dpm level for Vega12

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:43:09 -05:00
Evan Quan
b8a5559112 drm/amd/pp: use soc15 common macros instead of vega10 specific
pp_soc15.h is vega10 specific. Update powerplay code to use soc15 common
macros defined in soc15_common.h.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:43:04 -05:00
Rex Zhu
555fd70c59 drm/amd/pp: Not call cgs interface to get display info
DC/Non DC all will update display configuration
when the display state changed
No need to get display info through cgs interface

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-11 13:07:52 -05:00
Rex Zhu
29b443d016 drm/amd/pp: Remove Dead functions on Vega12
Remove Vega12 DIDT config functions.

Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-04-03 12:52:57 -05:00
Rex Zhu
bbfcc8af37 drm/amd/pp: Clean up powerplay code on Vega12
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-22 14:43:20 -05:00
Rex Zhu
4d2003721c drm/amd/pp: Refine register_thermal_interrupt function
v2: add Vega12 support

1. delete useless argument in function register_thermal_interrupt
2. rename function name register_thermal_interrupt to register_irq_handlers

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-21 14:36:58 -05:00
Rex Zhu
160b8e7593 drm/amdgpu: Remove wrapper layer of cgs irq handling
v2: add Vega12 support

1. remove struct cgs_os_ops
2. delete cgs_linux.h
3. refine the irq code for vega10, can fix set pp table
   failed issue.
4. add common smu irq process function

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-21 14:36:58 -05:00
Kenneth Feng
7436854ebd drm/amd/powerplay: Return per DPM level clock
Add change to return per DPM level clock in DAL interface

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-21 14:36:58 -05:00
Kenneth Feng
7f3f106e44 drm/amd/powerplay: Remove the SOC floor voltage setting
Remove W/A carried over from VG10 to set VDDSOC Floor Voltage
prior to enabling DPM since the VBIOS covers the floor voltage
setting now

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-21 14:36:57 -05:00
Evan Quan
2cac05dee6 drm/amd/powerplay: add the hw manager for vega12 (v4)
handles the driver power state setup

v2: squash in the following:
- handle negative temperature ranges
- add vega12 thermal ranges
- use ffs/fls
- remove ACG code
- resend NumOfDisplays message
- correct max dpm levels
- remove power containment settings
- fix warnings
- add sensors interface
- delete unused overdrive arbiter
- drop get_temperature callback
- smu table cleanup
- atomfirmware smu dpm table updates
v3: rebase
v4: rebase

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-03-21 14:36:56 -05:00