Marek Vasut
83b7a8e7e8
drm/panel/panel-sitronix-st7701: Parametrize voltage and timing
...
Instead of hard-coding TFT matrix voltage and timing settings, which can
even lead to permanent TFT matrix damage, parametrize them in TFT matrix
descriptor.
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Guido Günther <agx@sigxcpu.org >
Cc: Jagan Teki <jagan@amarulasolutions.com >
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Cc: Linus Walleij <linus.walleij@linaro.org >
Cc: Sam Ravnborg <sam@ravnborg.org >
Cc: Thierry Reding <thierry.reding@gmail.com >
Signed-off-by: Linus Walleij <linus.walleij@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220710194437.289042-8-marex@denx.de
2022-07-19 10:39:01 +02:00
Marek Vasut
de2b491784
drm/panel/panel-sitronix-st7701: Infer horizontal pixel count from TFT mode
...
The horizontal pixel count is a property of the TFT matrix. Currently the
driver hard-codes content of this register to specific value which is
only compatible with one TFT matrix, likely the TS8550B one.
Calculate the horizontal pixel count from the mode instead.
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Guido Günther <agx@sigxcpu.org >
Cc: Jagan Teki <jagan@amarulasolutions.com >
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Cc: Linus Walleij <linus.walleij@linaro.org >
Cc: Sam Ravnborg <sam@ravnborg.org >
Cc: Thierry Reding <thierry.reding@gmail.com >
Signed-off-by: Linus Walleij <linus.walleij@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220710194437.289042-7-marex@denx.de
2022-07-19 10:39:00 +02:00
Marek Vasut
82f9cee255
drm/panel/panel-sitronix-st7701: Adjust porch control bitfield name
...
Define DSI_CMD2_BK0_PORCTRL_VBP_MASK and DSI_CMD2_BK0_PORCTRL_VFP_MASK
and move the vertical back and front porch calculation from macros into
the st7701_init_sequence() function, so it is clear what this does.
No functional change.
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Guido Günther <agx@sigxcpu.org >
Cc: Jagan Teki <jagan@amarulasolutions.com >
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Cc: Linus Walleij <linus.walleij@linaro.org >
Cc: Sam Ravnborg <sam@ravnborg.org >
Cc: Thierry Reding <thierry.reding@gmail.com >
Signed-off-by: Linus Walleij <linus.walleij@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220710194437.289042-6-marex@denx.de
2022-07-19 10:38:59 +02:00
Marek Vasut
1ba85119af
drm/panel/panel-sitronix-st7701: Infer vertical line count from TFT mode
...
The vertical line count is a property of the TFT matrix. Currently the
driver hard-codes content of this register to specific value which is
only compatible with one TFT matrix, likely the TS8550B one.
Calculate the vertical line count from the mode instead.
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Guido Günther <agx@sigxcpu.org >
Cc: Jagan Teki <jagan@amarulasolutions.com >
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Cc: Linus Walleij <linus.walleij@linaro.org >
Cc: Sam Ravnborg <sam@ravnborg.org >
Cc: Thierry Reding <thierry.reding@gmail.com >
Signed-off-by: Linus Walleij <linus.walleij@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220710194437.289042-5-marex@denx.de
2022-07-19 10:38:57 +02:00
Marek Vasut
779c84fea3
drm/panel/panel-sitronix-st7701: Make gamma correction TFT specific
...
The gamma correction values are specific to the TFT which is attached to
the ST7701 TFT matrix driver, move the gamma correction values from what
incorrectly looks like common init sequence into TFT matrix specific
settings.
While doing so, add macros which defined fields within the gamma register
file and a macro which mimics FIELD_PREP except works with constant
expressions.
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Guido Günther <agx@sigxcpu.org >
Cc: Jagan Teki <jagan@amarulasolutions.com >
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Cc: Linus Walleij <linus.walleij@linaro.org >
Cc: Sam Ravnborg <sam@ravnborg.org >
Cc: Thierry Reding <thierry.reding@gmail.com >
Signed-off-by: Linus Walleij <linus.walleij@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220710194437.289042-4-marex@denx.de
2022-07-19 10:38:56 +02:00
Marek Vasut
7fa8e07128
drm/panel/panel-sitronix-st7701: Make voltage supplies common to ST7701
...
The ST7701 and ST7701S all have two voltage supplies, one for internal
logic and one for the TFT matrix driver. The supplies are not property
of the TFT matrix driver, so move them to common ST7701 code.
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Guido Günther <agx@sigxcpu.org >
Cc: Jagan Teki <jagan@amarulasolutions.com >
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Cc: Linus Walleij <linus.walleij@linaro.org >
Cc: Sam Ravnborg <sam@ravnborg.org >
Cc: Thierry Reding <thierry.reding@gmail.com >
Signed-off-by: Linus Walleij <linus.walleij@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220710194437.289042-3-marex@denx.de
2022-07-19 10:38:55 +02:00
Marek Vasut
a6c225be3d
drm/panel/panel-sitronix-st7701: Enable DSI burst mode, LPM, non-continuous clock
...
The ST7701(S) is capable of DSI burst mode, which is more energy
efficient than the non-burst modes. Make use of it.
The ST7701(S) is capable of DSI non-continuous clock, since it
sources the TFT matrix driver clock from internal clock source.
The DSI non-continuous clock further reduce power utilization.
The ST7701(S) uses DSI LPM for command transmissions, make sure
this is configured correctly in the DSI mode flags.
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Guido Günther <agx@sigxcpu.org >
Cc: Jagan Teki <jagan@amarulasolutions.com >
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Cc: Linus Walleij <linus.walleij@linaro.org >
Cc: Sam Ravnborg <sam@ravnborg.org >
Cc: Thierry Reding <thierry.reding@gmail.com >
Signed-off-by: Linus Walleij <linus.walleij@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220710194437.289042-2-marex@denx.de
2022-07-19 10:38:54 +02:00
Marek Vasut
6f481afe22
drm/panel/panel-sitronix-st7701: Make DSI mode flags common to ST7701
...
The ST7701 and ST7701S are TFT matrix drivers with integrated multi
protocol decoder capable of DSI/DPI/SPI input and 480x360...864 line
TFT matrix output. Currently the only supported input is DSI.
The protocol decoder is separate from the TFT matrix driver and is
always capable of handling all of DSI non-burst mode with sync pulses
or sync events as well as DSI burst mode.
Move the DSI mode configuration from TFT matrix driver properties to
common ST7701 code, because this is common to all TFT matrices.
Signed-off-by: Marek Vasut <marex@denx.de >
Cc: Guido Günther <agx@sigxcpu.org >
Cc: Jagan Teki <jagan@amarulasolutions.com >
Cc: Laurent Pinchart <laurent.pinchart@ideasonboard.com >
Cc: Linus Walleij <linus.walleij@linaro.org >
Cc: Sam Ravnborg <sam@ravnborg.org >
Cc: Thierry Reding <thierry.reding@gmail.com >
Reviewed-by: Linus Walleij <linus.walleij@linaro.org >
Signed-off-by: Linus Walleij <linus.walleij@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220710194437.289042-1-marex@denx.de
2022-07-19 10:38:52 +02:00
Swati Sharma
9899834ae5
drm/i915/display: Add debug print for scaler filter
...
Add debug print statement to print scaler filter property
value. Since property can be set as either default or integer
scaler; its good if we can get debug print for the same in dmesg
log.
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com >
Signed-off-by: Swati Sharma <swati2.sharma@intel.com >
Reviewed-by: Uma Shankar <uma.shankar@intel.com >
Signed-off-by: Uma Shankar <uma.shankar@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220706102240.21414-1-swati2.sharma@intel.com
2022-07-19 13:10:55 +05:30
shaomin Deng
3475b50873
drm:remove rebundant word "in" in comments
...
there is a repeated word "in", so remove it.
Signed-off-by: shaomin Deng <dengshaomin@cdjrlc.com >
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de >
Link: https://patchwork.freedesktop.org/patch/msgid/20220718150418.7321-1-dengshaomin@cdjrlc.com
2022-07-19 09:03:24 +02:00
shaomin Deng
71eed8a9ba
drm:delete the repeated word "the" in comments
...
remove the rebundant word "the" from comments.
Signed-off-by: shaomin Deng <dengshaomin@cdjrlc.com >
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de >
Link: https://patchwork.freedesktop.org/patch/msgid/20220718151154.9628-1-dengshaomin@cdjrlc.com
2022-07-19 09:03:24 +02:00
Kenneth Feng
a53bc32182
drm/amd/pm: enable mode1 reset for smu_v13_0_7
...
enable mode1 reset for smu_v13_0_7 since it's missing.
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com >
Reviewed-by: Yang Wang <kevinyang.wang@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
Hawking Zhang
5877b7ddbc
drm/amdgpu: correct the PSP_BL_CMD enum
...
To match with the enum defined in trusted os
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Le Ma <le.ma@amd.com >
Reviewed-by: John Clements <john.clements@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
Guchun Chen
9c913f3803
drm/amdgpu: drop runpm from amdgpu_device structure
...
It's redundant, as now switching to rpm_mode to indicate
runtime power management mode.
Suggested-by: Lijo Lazar <lijo.lazar@amd.com >
Signed-off-by: Guchun Chen <guchun.chen@amd.com >
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com >
Reviewed-by: Evan Quan <evan.quan@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
Guchun Chen
75a9ad8c1b
drm/amdgpu: drop runtime pm disablement quirk on several sienna cichlid cards
...
This quirk is not needed any more as it's fixed by bypassing
SMU FW reloading in runtime resume.
Signed-off-by: Guchun Chen <guchun.chen@amd.com >
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com >
Reviewed-by: Evan Quan <evan.quan@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
Guchun Chen
f746556aa9
drm/amdgpu: skip SMU FW reloading in runpm BACO case
...
SMU is always alive, so it's fine to skip SMU FW reloading
when runpm resumed from BACO, this can avoid some race issues
when resuming SMU.
Suggested-by: Evan Quan <evan.quan@amd.com >
Signed-off-by: Guchun Chen <guchun.chen@amd.com >
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com >
Reviewed-by: Evan Quan <evan.quan@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
Guchun Chen
50fe04d46a
drm/amdgpu: introduce runtime pm mode
...
It can benefit code consistency in future.
Suggested-by: Lijo Lazar <lijo.lazar@amd.com >
Signed-off-by: Guchun Chen <guchun.chen@amd.com >
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com >
Reviewed-by: Evan Quan <evan.quan@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
Dan Carpenter
2d04559e06
drm/amd/display: Remove unnecessary NULL check in commit_planes_for_stream()
...
Smatch complains that:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3369 commit_planes_for_stream()
warn: variable dereferenced before check 'stream' (see line 3114)
The 'stream' pointer cannot be NULL and the check can be removed.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
André Almeida
133dc89c64
drm/amdgpu: Clarify asics naming in Kconfig options
...
Clarify which architecture those asics acronyms refers to.
Signed-off-by: André Almeida <andrealmeid@igalia.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
Colin Ian King
606ee059f8
drm/amd/display: Fix spelling mistake "supporing" -> "supporting"
...
There is a spelling mistake in a dml_print message. Fix it.
Signed-off-by: Colin Ian King <colin.i.king@gmail.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:39 -04:00
Guenter Roeck
3876a8b5e2
drm/amd/display: Enable building new display engine with KCOV enabled
...
The new display engine uses floating point math, which is not supported
by KCOV. Commit 9d1d02ff369d1d02ff36arnd@arndb.de >
Cc: Leo Li <sunpeng.li@amd.com >
Reviewed-by: Harry Wentland <harry.wentland@amd.com >
Signed-off-by: Guenter Roeck <linux@roeck-us.net >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:38 -04:00
Alex Deucher
958afce98c
drm/amdgpu: restore original stable pstate on ctx fini
...
Save the original stable pstate on ctx init and restore
it on ctx fini so that we restore a manually selected
stable pstate on ctx exit.
v2: fix init order (Alex)
v3: don't add new variable to ctx struct (Evan)
Fixes: c65b364c52evan.quan@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:33 -04:00
Alex Deucher
98a90f1f0f
drm/amdgpu: use the same HDP flush registers for all nbio 2.3.x
...
Align RDNA2.x with other asics. One HDP bit per SDMA instance,
aligned with firmware. This is effectively a revert of
commit 369b7d04ba369b7d04bakent.russell@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:42:18 -04:00
Alex Deucher
912db6a587
drm/amdgpu: use the same HDP flush registers for all nbio 7.4.x
...
Align aldebaran with all other asics. One HDP bit per
SDMA instance, aligned with firmware. This is effectively
a revert of
commit a0f9f85466a0f9f85466kent.russell@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:41:55 -04:00
Vijendar Mukunda
4c33e5179f
drm/amdgpu: create I2S platform devices for Jadeite platform
...
Jadeite platform uses I2S MICSP instance.
Create platform devices for DMA controller and I2S controller for
Jadeite platform.
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:38:25 -04:00
Vijendar Mukunda
49062ee374
drm/amdgpu: add dmi check for jadeite platform
...
DMI check is required to distinguish Jadeite platform from
Stoney base variant.
Add DMI check logic for Jadeite platform.
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com >
Acked-by: Alex Deucher <alexander.deucher@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:38:19 -04:00
lin cao
748262eb40
drm/amdgpu: Call trace info was found in dmesg when loading amdgpu
...
In the case of SRIOV, the register smnMp1_PMI_3_FIFO will get an invalid
value which will cause the "shift out of bound". In Ubuntu22.04, this
issue will be checked an related call trace will be reported in dmesg.
Signed-off-by: lin cao <lin.cao@amd.com >
Reviewed-by: Jingwen Chen <Jingwen.Chen2@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:38:10 -04:00
Vijendar Mukunda
604d3a3f0d
drm/amdgpu: fix for coding style issues
...
Fixed below checkpatch warnings and errors
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:131: CHECK: Comparison to NULL could be written "apd"
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:150: CHECK: Comparison to NULL could be written "apd"
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:196: CHECK: Prefer kernel type 'u64' over 'uint64_t'
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:224: CHECK: Please don't use multiple blank lines
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:226: CHECK: Comparison to NULL could be written "!adev->acp.acp_genpd"
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:233: CHECK: Please don't use multiple blank lines
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:239: CHECK: Alignment should match open parenthesis
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:241: CHECK: Comparison to NULL could be written "!adev->acp.acp_cell"
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:247: CHECK: Comparison to NULL could be written "!adev->acp.acp_res"
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:253: CHECK: Comparison to NULL could be written "!i2s_pdata"
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:350: CHECK: Alignment should match open parenthesis
drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c:550: ERROR: that open brace { should be on the previous line
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com >
Reviewed-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:38:03 -04:00
YiPeng Chai
e4b1edf48f
drm/amdgpu: add umc ras functions for umc v8_10_0
...
1. Support query umc ras error counter.
2. Support ras umc ue error address remapping.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com >
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Tao Zhou <tao.zhou1@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:37:47 -04:00
YiPeng Chai
75510fac07
drm/amdgpu: add umc v8_10_0 ip headers
...
Add umc v8_10_0 register offset and shift masks
header files
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com >
Reviewed-by: Alexander Deucher <Alexander.Deucher@amd.com >
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com >
Reviewed-by: Tao Zhou <tao.zhou1@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:37:38 -04:00
Andrey Grodzovsky
f6a3f66063
drm/amdgpu: Get rid of amdgpu_job->external_hw_fence
...
This is a follow-up cleanup to [1]. See bellow refcount balancing
for calling amdgpu_job_submit_direct after this cleanup as far
as I calculated.
amdgpu_fence_emit
dma_fence_init 1
dma_fence_get(fence) 2
rcu_assign_pointer(*ptr, dma_fence_get(fence) 3
---> amdgpu_job_submit_direct completes before fence signaled
amdgpu_sa_bo_free
(*sa_bo)->fence = dma_fence_get(fence) 4
amdgpu_job_free
dma_fence_put 3
amdgpu_vcn_enc_get_destroy_msg
*fence = dma_fence_get(f) 4
dma_fence_put(f); 3
amdgpu_vcn_enc_ring_test_ib
dma_fence_put(fence) 2
amdgpu_fence_process
dma_fence_put 1
amdgpu_sa_bo_remove_locked
dma_fence_put 0
---> amdgpu_job_submit_direct completes after fence signaled
amdgpu_fence_process
dma_fence_put 2
amdgpu_job_free
dma_fence_put 1
amdgpu_vcn_enc_get_destroy_msg
*fence = dma_fence_get(f) 2
dma_fence_put(f); 1
amdgpu_vcn_enc_ring_test_ib
dma_fence_put(fence) 0
[1] - https://patchwork.kernel.org/project/dri-devel/cover/20220624180955.485440-1-andrey.grodzovsky@amd.com/
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com >
Suggested-by: Christian König <christian.koenig@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:37:25 -04:00
Sonny Jiang
0b15205c73
drm/amdgpu: limiting AV1 to first instance on VCN4 decode
...
AV1 is only supported on first instance.
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com >
Reviewed-by: James Zhu <James.Zhu@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 16:37:09 -04:00
shaomin Deng
2b066860a4
drm/mgag200:remove rebundant word "or" in comments
...
there is a repeated word "or" in comments, so remove it.
Signed-off-by: shaomin Deng <dengshaomin@cdjrlc.com >
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de >
Link: https://patchwork.freedesktop.org/patch/msgid/20220718145536.4866-1-dengshaomin@cdjrlc.com
2022-07-18 18:44:01 +02:00
xinhui pan
e1aadbab44
drm/amdgpu: Remove one duplicated ef removal
...
That has been done in BO release notify.
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2074
Signed-off-by: xinhui pan <xinhui.pan@amd.com >
Acked-by: Christian König <christian.koenig@amd.com >
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-18 11:45:23 -04:00
José Roberto de Souza
031a2fea04
drm/i915/psr: Disable PSR before disable pipe
...
The issue here was on for_each_intel_encoder_mask_with_psr() over the
new_crtc_state encoder mask, so if the CRTC was being disabled mask
would be zero and it would not have any chance to disable PSR.
So here doing for_each_intel_encoder_mask_with_psr() over the
old_crtc_state encoder mask and then using the new_crtc_state to
check if PSR needs to be disabled.
Cc: Jouni Högander <jouni.hogander@intel.com >
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Jouni Högander <jouni.hogander@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220714150755.154985-2-jose.souza@intel.com
2022-07-18 06:53:38 -07:00
José Roberto de Souza
ad444123a4
Revert "drm/i915/display: Ensure PSR gets disabled if no encoders in new state"
...
This patches fixes a issue but not in the right way as
for_each_oldnew_intel_crtc_in_state() will interate over all CRTCs
not only the crtc passed as parameter, also this two for_each loops
are not necessary and only make code harder to understand.
Proper fix will be discussed in the next patch.
This reverts commit 75f664903djouni.hogander@intel.com >
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com >
Signed-off-by: José Roberto de Souza <jose.souza@intel.com >
Reviewed-by: Jouni Högander <jouni.hogander@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220714150755.154985-1-jose.souza@intel.com
2022-07-18 06:53:37 -07:00
Imre Deak
c19491894d
drm/i915/tgl+: Fix HDMI transcoder clock vs. DDI BUF disabling order
...
Starting with TGL the disabling order of HDMI transcoder clock vs. DDI
BUF has swapped, fix this. There hasn't been any issues seen related to
this, but let's follow the spec.
Reported-by: Sandeep K Lakkakula <sandeep.k.lakkakula@intel.com >
Signed-off-by: Imre Deak <imre.deak@intel.com >
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220617112807.1586621-1-imre.deak@intel.com
2022-07-18 15:17:41 +03:00
allen chen
1a217205bd
drm/bridge: it6505: Modified video clock calculation and video debug message
...
Speed up video clock calculation and remove redundant video debug message.
Signed-off-by: Pin-Yen Lin <treapking@chromium.org >
Signed-off-by: Allen Chen <allen.chen@ite.com.tw >
Reviewed-by: Robert Foss <robert.foss@linaro.org >
Signed-off-by: Robert Foss <robert.foss@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220715024910.12578-4-allen.chen@ite.com.tw
2022-07-18 13:43:19 +02:00
allen chen
86088f88a2
drm/bridge: it6505: Add i2c api power on check
...
Use i2c bus to read/write when it6505 power off will occur i2c error.
Add this check will prevent i2c error when it6505 power off.
Signed-off-by: Pin-Yen Lin <treapking@chromium.org >
Signed-off-by: Allen Chen <allen.chen@ite.com.tw >
Reviewed-by: Robert Foss <robert.foss@linaro.org >
Signed-off-by: Robert Foss <robert.foss@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220715024910.12578-3-allen.chen@ite.com.tw
2022-07-18 13:43:18 +02:00
allen chen
899e90cf20
drm/bridge: it6505: Modified power sequence
...
Change power sequence to meet it6505 data sheet requirement when boot on.
Signed-off-by: Pin-Yen Lin <treapking@chromium.org >
Signed-off-by: Allen Chen <allen.chen@ite.com.tw >
Reviewed-by: Robert Foss <robert.foss@linaro.org >
Signed-off-by: Robert Foss <robert.foss@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220715024910.12578-2-allen.chen@ite.com.tw
2022-07-18 13:43:17 +02:00
Pin-Yen Lin
fbc1fdaa83
drm/bridge: it6505: Power on downstream device in .atomic_enable
...
Send DPCD DP_SET_POWER_D0 command to the monitor in .atomic_enable
callback. Without this command, some monitors won't show up again after
changing the resolution.
Fixes: 46ca7da7f1treapking@chromium.org >
Reviewed-by: Allen Chen <allen.chen@ite.com.tw >
Fixes: 46ca7da7f1robert.foss@linaro.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220714173715.v2.1.I85af54e9ceda74ec69f661852825845f983fc343@changeid
2022-07-18 13:27:23 +02:00
Javier Martinez Canillas
6fc20a8592
drm/ssd130x: Use new regmap bulk write support to drop custom bus
...
Data writes for the ssd130x 4-wire SPI protocol need special handling, due
the Data/Command control (D/C) pin having to be toggled prior to the write.
The regmap API only allowed drivers to provide .reg_{read,write} callbacks
to do per register read/write, but didn't provide a way for drivers to do
the same for bulk read/writes.
For this reason, a custom regmap bus was used by the driver just to define
a bulk write callback that implements the D/C pin toggling. But the regmap
API has been extended to support defining bulk read/write handlers, so the
custom regmap bus is not needed anymore and could just be dropped.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com >
Acked-by: Sam Ravnborg <sam@ravnborg.org >
Link: https://patchwork.freedesktop.org/patch/msgid/20220618174338.2253021-1-javierm@redhat.com
2022-07-18 10:38:42 +02:00
Christian König
dbd0da2453
drm/ttm: fix locking in vmap/vunmap TTM GEM helpers
...
I've stumbled over this while reviewing patches for DMA-buf and it looks
like we completely messed the locking up here.
In general most TTM function should only be called while holding the
appropriate BO resv lock. Without this we could break the internal
buffer object state here.
Only compile tested!
Signed-off-by: Christian König <christian.koenig@amd.com >
Fixes: 43676605f8stable@vger.kernel.org
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220715111533.467012-1-christian.koenig@amd.com
2022-07-18 09:18:53 +02:00
Alex Sierra
c83dee9b63
drm/amdkfd: add SPM support for SVM
...
When CPU is connected throug XGMI, it has coherent access to VRAM
resource. In this case that resource is taken from a table in the device
gmc aperture base. This resource is used along with the device type,
which could be DEVICE_PRIVATE or DEVICE_COHERENT to create the device page
map region.
Also, MIGRATE_VMA_SELECT_DEVICE_COHERENT flag is selected for coherent
type case during migration to device.
Link: https://lkml.kernel.org/r/20220715150521.18165-8-alex.sierra@amd.com
Signed-off-by: Alex Sierra <alex.sierra@amd.com >
Signed-off-by: Christoph Hellwig <hch@lst.de >
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com >
Cc: Alistair Popple <apopple@nvidia.com >
Cc: David Hildenbrand <david@redhat.com >
Cc: Jason Gunthorpe <jgg@nvidia.com >
Cc: Jerome Glisse <jglisse@redhat.com >
Cc: Matthew Wilcox <willy@infradead.org >
Cc: Ralph Campbell <rcampbell@nvidia.com >
Signed-off-by: Andrew Morton <akpm@linux-foundation.org >
2022-07-17 17:14:28 -07:00
Linus Torvalds
55ea9bd666
Merge tag 'drm-intel-fixes-2022-07-17' of git://anongit.freedesktop.org/drm/drm-intel
...
Pull intel drm build fix from Rodrigo Vivi:
"Our 'dim' flow has a problem with fixes of fixes getting missed. We
need to take a look on that later.
Meanwhile, please allow me to quickly propagate this fix for the
32-bit build issue here upstream"
* tag 'drm-intel-fixes-2022-07-17' of git://anongit.freedesktop.org/drm/drm-intel:
drm/i915/ttm: fix 32b build
2022-07-17 13:08:03 -07:00
Matthew Auld
ced7866db3
drm/i915/ttm: fix 32b build
...
Since segment_pages is no longer a compile time constant, it looks the
DIV_ROUND_UP(node->size, segment_pages) breaks the 32b build. Simplest
is just to use the ULL variant, but really we should need not need more
than u32 for the page alignment (also we are limited by that due to the
sg->length type), so also make it all u32.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com >
Fixes: aff1e0b09bmatthew.auld@intel.com >
Cc: Nirmoy Das <nirmoy.das@linux.intel.com >
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220712174050.592550-1-matthew.auld@intel.com
(cherry picked from commit 9306b2b2dfrodrigo.vivi@intel.com >
2022-07-17 14:53:47 -04:00
Jason A. Donenfeld
868941b144
fs: remove no_llseek
...
Now that all callers of ->llseek are going through vfs_llseek(), we
don't gain anything by keeping no_llseek around. Nothing actually calls
it and setting ->llseek to no_lseek is completely equivalent to
leaving it NULL.
Longer term (== by the end of merge window) we want to remove all such
intializations. To simplify the merge window this commit does *not*
touch initializers - it only defines no_llseek as NULL (and simplifies
the tests on file opening).
At -rc1 we'll need do a mechanical removal of no_llseek -
git grep -l -w no_llseek | grep -v porting.rst | while read i; do
sed -i '/\<no_llseek\>/d' $i
done
would do it.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com >
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk >
2022-07-16 09:19:47 -04:00
Sam Ravnborg
5f9cfd8243
drm/via: Fix style issues in via_3d_reg header
...
- Fix comments using wrong style
- Drop repeated word
This fixes all checkpatch complains and makes the file a little
bit easier to read - as the eye is not distracted by the style
violations.
Suggested-by: Thomas Zimmermann <tzimmermann@suse.de >
Signed-off-by: Sam Ravnborg <sam@ravnborg.org >
Acked-by: Thomas Zimmermann <tzimmermann@suse.de >
Cc: Kevin Brace <kevinbrace@bracecomputerlab.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220713170202.1798216-14-sam@ravnborg.org
2022-07-16 09:32:20 +02:00
Sam Ravnborg
3579ca9575
drm/via: Make macros readable in the via_3d_reg header
...
The macros for texture 1 setting all used continuation on a new line,
resulting in a highly ureadable definition.
Merge the lines so they are each on a single line.
As a nice side-effect this fixes a number of checkpatch warnings:
"WARNING: please, no spaces at the start of a line".
Suggested-by: Thomas Zimmermann <tzimmermann@suse.de >
Signed-off-by: Sam Ravnborg <sam@ravnborg.org >
Acked-by: Thomas Zimmermann <tzimmermann@suse.de >
Cc: Kevin Brace <kevinbrace@bracecomputerlab.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220713170202.1798216-13-sam@ravnborg.org
2022-07-16 09:32:13 +02:00
Sam Ravnborg
e1df7580bb
drm/via: Use SPDX tag for MIT license in via_3d_reg header
...
The license for the via_3d_reg header is MIT - so use the
shorter SPDX tag to identify the license.
Suggested-by: Thomas Zimmermann <tzimmermann@suse.de >
Signed-off-by: Sam Ravnborg <sam@ravnborg.org >
Acked-by: Thomas Zimmermann <tzimmermann@suse.de >
Cc: Kevin Brace <kevinbrace@bracecomputerlab.com >
Link: https://patchwork.freedesktop.org/patch/msgid/20220713170202.1798216-12-sam@ravnborg.org
2022-07-16 09:27:17 +02:00
