Benjamin Gaignard
39434d42e8
media: hantro: Allows luma and chroma depth to be different
...
Luma and chroma depth are set on different hardware registers.
Even if they aren't identical the bitstream can be compliant
to HEVC specifications and decoded by the hardware.
With this patch TSUNEQBD_A_MAIN10_Technicolor_2 conformance test
is successfully decoded.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com >
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar >
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl >
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org >
2022-09-24 09:01:15 +02:00
Benjamin Gaignard
dc39473d03
media: hantro: imx8m: Enable 10bit decoding
...
Expose 10bit pixel formats to enable 10bit decoding in IMX8M SoCs.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com >
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar >
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl >
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org >
2022-09-24 09:00:50 +02:00
Benjamin Gaignard
d040a24b5a
media: Hantro: HEVC: Allows 10-bit bitstream
...
Stop limiting HEVC support to 8-bits bitstreams also
accept 10-bits bitstreams.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com >
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar >
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl >
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org >
2022-09-24 09:00:27 +02:00
Benjamin Gaignard
5aa24d7299
media: hantro: postproc: Configure output regs to support 10bit
...
Move output format setting in postproc and make sure that
8/10bit configuration is correctly set.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com >
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar >
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl >
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org >
2022-09-24 09:00:00 +02:00
Benjamin Gaignard
f64853ad7f
media: hantro: HEVC: Fix chroma offset computation
...
The chroma offset depends of the bitstream depth.
Make sure that ctx->bit_depth is used to compute it.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com >
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar >
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl >
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org >
2022-09-24 08:59:05 +02:00
Benjamin Gaignard
8a438580a0
media: hantro: HEVC: Fix auxilary buffer size calculation
...
SAO and FILTER buffers size depend of the bit depth.
Make sure we have enough space for 10bit bitstreams.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com >
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar >
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl >
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org >
2022-09-24 08:58:12 +02:00
Benjamin Gaignard
4bec03301e
media: hantro: Store HEVC bit depth in context
...
Store HEVC bit depth in context.
Bit depth is equal to hevc sps bit_depth_luma_minus8 + 8.
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com >
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar >
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl >
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org >
2022-09-24 08:57:32 +02:00
Ezequiel Garcia
fbb6c848dd
media: destage Hantro VPU driver
...
The Hantro mainline driver has been used in production
since several years and was only kept as a staging driver
due the stateless CODEC controls.
Now that all the stateless CODEC controls have been moved
out of staging, graduate the driver as well.
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar >
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl >
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org >
2022-08-31 10:23:50 +02:00
