Pull clk updates from Stephen Boyd:
"Not much changed in the clk framework this time except the clk.h
consumer API moved the context saving APIs around to fix a build error
in certain configurations.
There was a change to the core framework for CLK_OPS_PARENT_ENABLE
behavior during registration, but it wrecked existing drivers that
didn't expect things to be turned off during clk registration so it
got reverted.
This cycle is really a large collection of new clk drivers, primarily
for Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed.
Another big change in here is support for automatic hardware clock
gating on Samsung SoCs where the clks turn on and off when needed.
Ideally more vendors move to this method for better power savings. The
highlights are in the updates section below.
Beyond all the new drivers we have a bunch of cleanups like converting
drivers from divider_round_rate() to divider_determine_rate() and
using scoped for each OF child loops. Otherwise it's the usual data
fixes and plugging reference leaks, etc. that's all pretty ordinary
but not critical enough to fix until the next release.
New Drivers:
- Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and
video clk controllers
- Qualcomm SM8750 camera clk controllers
- Qualcomm MSM8940 and SDM439 global clk controllers
- Google GS101 Display Process Unit (DPU) clk controllers
- SpacemiT K3 clk controllers
- Amlogic t7 clk controllers
- Aspeed AST2700 clk controllers
Updates:
- Convert clock dividers from round_rate() to determine_rate()
- Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
- Automatic hardware clk gating on Google GS101 SoCs
- Amlogic s4 video clks
- CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and
RZ/V2N
- Expanded Serial Peripheral Interface (xSPI) clocks and resets on
Renesas RZ/T21H and RZ/N2H
- DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and
resets on Renesas RZ/V2N
- More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
- CPU frequency scaling on T-HEAD TH1520"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (165 commits)
clk: aspeed: Add reset for HACE/VIDEO
dt-bindings: clock: aspeed: Add VIDEO reset definition
clk: aspeed: add AST2700 clock driver
MAINTAINERS: Add entry for ASPEED clock drivers.
clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.
Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
clk: Disable KUNIT_UML_PCI
dt-bindings: clk: rs9: Fix DIF pattern match
clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc
clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
clk: mediatek: Fix error handling in runtime PM setup
clk: mediatek: don't select clk-mt8192 for all ARM64 builds
clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
clk: mediatek: Refactor pllfh registration to pass device
clk: mediatek: Pass device to clk_hw_register for PLLs
clk: mediatek: Refactor pll registration to pass device
clk: Respect CLK_OPS_PARENT_ENABLE during recalc
...
* clk-imx:
clk: imx: fracn-gppll: Add 241.90 MHz Support
clk: imx: fracn-gppll: Add 332.60 MHz Support
* clk-divider:
rtc: ac100: convert from divider_round_rate() to divider_determine_rate()
clk: zynqmp: divider: convert from divider_round_rate() to divider_determine_rate()
clk: x86: cgu: convert from divider_round_rate() to divider_determine_rate()
clk: versaclock3: convert from divider_round_rate() to divider_determine_rate()
clk: stm32: stm32-core: convert from divider_round_rate_parent() to divider_determine_rate()
clk: stm32: stm32-core: convert from divider_ro_round_rate() to divider_ro_determine_rate()
clk: sprd: div: convert from divider_round_rate() to divider_determine_rate()
clk: sophgo: sg2042-clkgen: convert from divider_round_rate() to divider_determine_rate()
clk: nxp: lpc32xx: convert from divider_round_rate() to divider_determine_rate()
clk: nuvoton: ma35d1-divider: convert from divider_round_rate() to divider_determine_rate()
clk: milbeaut: convert from divider_round_rate() to divider_determine_rate()
clk: milbeaut: convert from divider_ro_round_rate() to divider_ro_determine_rate()
clk: loongson1: convert from divider_round_rate() to divider_determine_rate()
clk: hisilicon: clkdivider-hi6220: convert from divider_round_rate() to divider_determine_rate()
clk: bm1880: convert from divider_round_rate() to divider_determine_rate()
clk: bm1880: convert from divider_ro_round_rate() to divider_ro_determine_rate()
clk: actions: owl-divider: convert from divider_round_rate() to divider_determine_rate()
clk: actions: owl-composite: convert from owl_divider_helper_round_rate() to divider_determine_rate()
clk: sunxi-ng: convert from divider_round_rate_parent() to divider_determine_rate()
clk: sophgo: cv18xx-ip: convert from divider_round_rate() to divider_determine_rate()
* clk-rockchip:
clk: rockchip: Fix error pointer check after rockchip_clk_register_gate_link()
* clk-microchip:
dt-bindings: clock: mpfs-clkcfg: Add pic64gx compatibility
dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility
clk: microchip: drop POLARFIRE from ARCH_MICROCHIP_POLARFIRE
clk: microchip: core: remove unused include asm/traps.h
clk: microchip: core: correct return value on *_get_parent()
clk: microchip: core: remove duplicate determine_rate on pic32_sclk_ops
The pattern match [0-19] is incorrect and does not cover range of 0..19,
use pattern 1?[0-9] to cover range 0..19 instead. Update the example to
validate all parts of the pattern match and prevent such failures in the
future.
Fixes: 26c1bc67aa ("dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator")
Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Samsung DTS ARM64 changes for v6.20, part two
Add DPU clock management unit nodes to Google GS101.
* tag 'samsung-dt64-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes
dt-bindings: clock: google,gs101-clock: Add DPU clock management unit
dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Qualcomm Arm64 DeviceTree for v6.20
Introduce the Kaanapali SoC, with the MTP and QRD devices. Introduce
support for the Milos SoC (SM7635) and initial support for the Fairphone
(Gen 6) device on this platform.
Add the QCS6490-based RubikPI3 board, the QRB2210-based Arduino UnoQ,
the X Elite-based Medion SPRCHRGD 14 S1 and Surface Pro 11 laptops, and
the SDM845-based Pixel 3 and Pixel 3 XL devices.
On the Kodiak-based (QCS6490) RB3Gen2 the TC9563 PCIe switch controller
is described.
On Lemans (SA8775P/QCS9075) the GPU and crypto blocks are added.
IO-regions and clocks are added to interconnect nodes to allow QoS
configuration. GPU, TPM and USB support are enabled on the evaluation
kit (EVK).
On Monaco (QCS8300) the two PCIe controllers, the camera subsystem,
tsens, display subsystem, crypto, CPUfreq, and coresight are added. On
the evaluation kit (EVK) the PCIe busses are enabled, together with an
AMC6821-based fan controller and the ST33 TPM chip.
On MSM8939 the camera subsystem is described. The Asus ZenFone 2
Laser/Selfie gains battery and hall sensor support.
On the Agatti-based RB1 board PM8008 is described and an overlay for the
Vision mezzanine is introduced.
On SDM630 the compute DSP remoteproc, FastRPC and related entites are
described. The LPASS LPI pinctrl node is described.
On SDM845-based OnePlus device the bootloader framebuffer and its
resources are described, to improve the transition. On the SDM845-based
devices from OnePlus, SHIFT, and Xiaomi ath10k calibration variants are
specified. The sensor remoteproc is enabled on Xiaomi Pocophone F1.
On SM7225-based Fairphone FP4 regulators for the cameras are described,
and the camera EEPROM is added.
On SM8650 the camera subsystem is described. On the QRD the Samsung
S5KJN1 camera sensor is added, and for the HDK an overlay for the "Rear
Camera Card" is added.
On SM8750 CPUfreq, SDCHCI and Iris (video encode/decode) support are
added, and missing - required - properties for the BAM DMA is added.
These are then enabled on the MTP.
On Talos (SM6150/QCS615) PMU, DisplayPort, and USB/DP combo PHY are added.
DisplayPort is enabled on the Talos Ride board.
On Hamoa (X Elite) add crypto engine, missing TCSR reference clocks, and
random number generator block. The soc bus address width is corrected to
match the hardware. On the Lenovo Thinkpad T14s HDMI and audio playback
over DisplayPort is introduced. HDMI, Iris (video encode/decode) and
PS8830 retimers are described for the ASUS Vivobook S 15. On the Hamoa
evaluation kit (EVK) PCIe busses, WiFi, backlight, TPM and RG
(red/green) LEDs are described.
Enable QSEECOM, and thereby UEFI variable access, on the Medion SPRCHRGD
14 S1 (commit should have been on drivers branch).
* tag 'qcom-arm64-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (155 commits)
dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms
dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for Kaanapali
arm64: dts: qcom: lemans: enable static TPDM
arm64: dts: qcom: kodiak: Add memory region for audiopd
arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: add HDMI nodes
arm64: dts: qcom: x1e: bus is 40-bits (fix 64GB models)
arm64: dts: qcom: lemans; Add EL2 overlay
arm64: dts: qcom: sm8150: add uart13
arm64: dts: qcom: sdm845-db845c: specify power for WiFi CH1
arm64: dts: qcom: sdm845-db845c: drop CS from SPIO0
arm64: dts: qcom: qrb4210-rb2: Fix UART3 wakeup IRQ storm
arm64: dts: qcom: sm6125-ginkgo: Fix missing msm-id subtype
arm64: dts: qcom: qcs8300: Add GPU cooling
arm64: dts: qcom: sa8775p: Add reg and clocks for QoS configuration
arm64: dts: qcom: hamoa-iot-evk: Enable TPM (ST33) on SPI11
arm64: dts: qcom: talos: Add PMU support
arm64: dts: qcom: talos: switch to interrupt-cells 4 to add PPI partitions
arm64: dts: qcom: ipq9574: Complete USB DWC3 wrapper interrupts
arm64: dts: qcom: ipq5018: Correct USB DWC3 wrapper interrupts
arm64: dts: qcom: monaco: Add CTCU and ETR nodes
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The PCIESYS register space contains a pure clock controller, which
has no system controller register, so this definitely doesn't need
any "syscon" compatible.
As a side note, luckily no devicetree ever added the syscon string
to PCIESYS clock controller node compatibles, so this also resolves
a dtbs_check warning for mt7622.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add compatible strings for clock drivers to support Spacemit K3 SoC,
also includes all the defined clock IDs.
The SpacemiT K3 SoC clock IP is scattered over several different blocks,
which are APBC, APBS, APMU, DCIU, MPMU, all of them are capable of
generating clock and reset signals. APMU and MPMU have additional Power
Domain management functionality.
Following is a brief list that shows devices managed in each block:
APBC: UART, GPIO, PWM, SPI, TIMER, I2S, IR, DR, TSEN, IPC, CAN
APBS: various PPL clocks control
APMU: CCI, CPU, CSI, ISP, LCD, USB, QSPI, DMA, VPU, GPU, DSI, PCIe, EMAC..
DCID: SRAM, DMA, TCM
MPMU: various PLL1 derived clocks, UART, WATCHDOG, I2S
Link: https://lore.kernel.org/r/20260108-k3-clk-v5-1-42a11b74ad58@gentoo.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
Merge the Kaanapali camera, display, GPU, and video clock controller
bindings through a topic branch, to allow making them available to the
DeviceTree branch as well.
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
Power domains (GDSC), but the requirement from the SW driver is to use
the GDSC power domain from the clock controller to recover the GPU
firmware in case of any failure/hangs. The rest of the resources of the
clock controller are being used by the firmware of GPU. This module
exposes the GDSC power domains which helps the recovery of Graphics
subsystem.
Add bindings documentation for the Kaanapali Graphics Clock and Graphics
power domain Controller for Kaanapali SoC.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260107-kaanapali-mmcc-v3-v3-7-8e10adc236a8@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Merge the SM8750 camera clock controller binding through a topic branch,
in order to allow the defines to made availabe to the DeviceTree
branch as well.
Each CMU (with the exception of cmu_top) has a corresponding sysreg bank
that contains the BUSCOMPONENT_DRCG_EN and optional MEMCLK registers.
The BUSCOMPONENT_DRCG_EN register enables dynamic root clock gating of
bus components and MEMCLK gates the sram clock.
Now the clock driver supports automatic clock mode, to fully enable dynamic
root clock gating it is required to configure these registers. Update the
bindings documentation so that all CMUs (with the exception of
gs101-cmu-top) have samsung,sysreg as a required property.
Note this is NOT an ABI break, as if the property isn't specified the
clock driver will fallback to the current behaviour of not initializing
the registers. The system still boots, but bus components won't benefit
from dynamic root clock gating and dynamic power will be higher (which has
been the case until now anyway).
Additionally update the DT example to included the correct CMU size as
registers in that region are used for automatic clock mode.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20251222-automatic-clocks-v7-1-fec86fa89874@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Pull pin control updates from Linus Walleij:
"The technical details below. For me the CIX Semi and Axis
Communications ARTPEC-9 SoCs were the most interesting new drivers in
this merge window.
Core changes:
- Handle per-direction skew control in the generic pin config
- Drop the pointless subsystem boilerplate banner message during
boot. Less noise in the console. It's available as debug message if
someone really want it
New drivers:
- Samsung Exynos 8890 SoC support
- Samsung Exynos derived Axis Communications ARTPEC-9 SoC support.
These guys literally live next door to me, ARTPEC spells out "Axis
Real-Time Picture Encoding Chip" and is tailored for camera image
streams and is something they have evolved for a quarter of a
century
- Mediatek MT6878 SoC support
- Qualcomm Glymur PMIC support (mostly just compatible strings)
- Qualcomm Kaanapali SoC TLMM support
- Microchip pic64gx "gpio2" SoC support
- Microchip Polarfire "iomux0" SoC support
- CIX Semiconductors SKY1 SoC support
- Rockchip RK3506 SoC support
- Airhoa AN7583 chip support
Improvements:
- Improvements for ST Microelectronics STM32 handling of skew
settings so input and output can have different skew settings
- A whole bunch of device tree binding cleanups: Marvell Armada and
Berlin, Actions Semiconductor S700 and S900, Broadcom Northstar 2
(NS2), Bitmain BM1880 and Spreadtrum SC9860 are moved over to
schema"
* tag 'pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits)
pinctrl: add CONFIG_OF dependencies for microchip drivers
pinctrl: starfive: use dynamic GPIO base allocation
pinctrl: single: Fix incorrect type for error return variable
MAINTAINERS: Change Linus Walleij mail address
pinctrl: cix: Fix obscure dependency
dt-bindings: pinctrl: cix,sky1-pinctrl: Drop duplicate newline
dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group
pinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data
pinctrl: airoha: fix pinctrl function mismatch issue
pinctrl: cherryview: Convert to use intel_gpio_add_pin_ranges()
pinctrl: intel: Export intel_gpio_add_pin_ranges()
pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling
pinctrl: airoha: convert comma to semicolon
pinctrl: elkhartlake: Switch to INTEL_GPP() macro
pinctrl: cherryview: Switch to INTEL_GPP() macro
pinctrl: emmitsburg: Switch to INTEL_GPP() macro
pinctrl: denverton: Switch to INTEL_GPP() macro
pinctrl: cedarfork: Switch to INTEL_GPP() macro
pinctrl: airoha: add support for Airoha AN7583 PINs
dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller
...
Pull clk updates from Stephen Boyd:
"This is entirely SoC clk drivers.
The majority diff wise is for the new Rockchip and Qualcomm clk
drivers which is mostly lines and lines of data structures to describe
the clk hardware in these SoCs. Beyond those two, Renesas continues to
incrementally add clks to their SoC drivers, causing them to show up
higher in the diffstat this time because they added quite a few clks
all over the place.
Overall it is a semi-quiet release that has some new clk drivers and
the usual fixes for clock data that was wrong or missing and
non-critical cleanups that plug error paths or fix typos.
New Drivers:
- Qualcomm IPQ5424 Network Subsystem Clock Controller
- Qualcomm SM8750 Video Clock Controller
- Rockchip RV1126B and RK3506 clock drivers
- i.MX8ULP SIM LPAV clock driver
- Samsung ACPM (firmware interface) clock driver
- Altera Agilex5 clock driver"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (117 commits)
clk: keystone: fix compile testing
clk: keystone: syscon-clk: fix regmap leak on probe failure
clk: qcom: Mark camcc_sm7150_hws static
clk: samsung: exynos-clkout: Assign .num before accessing .hws
clk: rockchip: Add clock and reset driver for RK3506
dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
clk: actions: Fix discarding const qualifier by 'container_of' macro
clk: spacemit: Set clk_hw_onecell_data::num before using flex array
clk: visconti: Add VIIF clocks
dt-bindings: clock: tmpv770x: Add VIIF clocks
dt-bindings: clock: tmpv770x: Remove definition of number of clocks
clk: visconti: Do not define number of clocks in bindings
clk: rockchip: Add clock controller for the RV1126B
dt-bindings: clock, reset: Add support for rv1126b
clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll()
clk: qcom: x1e80100-dispcc: Add USB4 router link resets
dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets
clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750
dt-bindings: clock: qcom: Add SM8750 video clock controller
clk: qcom: branch: Extend invert logic for branch2 mem clocks
...
Pull SoC devicetree updates from Arnd Bergmann:
"Three new SoCs got added in existing arm64 chip families:
- Renesas R-Car X5H (R8A78000) is a new generation of automotive
SoCs, based on 16 Cortex-A720 (Armv9.2) cores, which makes the the
currently highest-perforance embedded SoC.
- TI AM62L is a new variant of the AM62 family of industrial SoCs,
this one comes without a GPU.
- Qualcomm MSM8937 (Snapdragon 430) is an older mobile phone chip
based on Cortex-A53, and closely related to MSM8917 (Snapdragn
425), which we already support.
In addition, there are a good number of newly supported machines
across SoC families:
- Two Aspeed AST2600 (Cortex-A7) based BMC setups for large servers
- Mobile Phones and tables based on Mediatek MT6582, Nvidia Tegra124,
Qualcomm MSM8937 and Qualcomm MSM8939,
- Two Laptops based on Qualcomm SoCs: one using the older sdm850, the
other using x1p42100.
- One Router based on Rockchips RK3568
- 24 variants of the Enclustra Mercury system-on-module, all based on
32-bit Intel/Altera SocFPGA chips, plus two boards using 64-bit
SocFPGA Agilex chips..
- 30 industrial/embedded boards and single-board computers, using
various chips from NXP, Rockchips, Mediatek, TI, Amlogic, Qualcomm,
Spacemit, and Starfive.
In total there are 783 commits here, the majority of these improving
hardware support and cleaning up devicetree files across the tree,
with the majority of the changes going into the Qualcomm, NXP, Renesas
and Rockchips platforms"
* tag 'soc-dt-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (782 commits)
arm64: dts: mediatek: mt8195: Fix address range for JPEG decoder core 1
ARM: dts: samsung: exynos4412-midas: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-trats: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: exynos4210-i9100: turn off SDIO WLAN chip during system suspend
ARM: dts: samsung: universal_c210: turn off SDIO WLAN chip during system suspend
arm64: dts: amlogic: meson-g12b: Fix L2 cache reference for S922X CPUs
arm64: dts: Add gpio_intc node for Amlogic S7D SoCs
arm64: dts: Add gpio_intc node for Amlogic S7 SoCs
arm64: dts: Add gpio_intc node for Amlogic S6 SoCs
arm64: dts: amlogic: s7d: add ao secure node
arm64: dts: amlogic: s7: add ao secure node
arm64: dts: amlogic: s6: add ao secure node
arm64: dts: amlogic: Fix the register name of the 'DBI' region
dts: arm64: amlogic: add a5 pinctrl node
arm64: dts: amlogic: s7d: add power domain controller node
arm64: dts: amlogic: s7: add power domain controller node
arm64: dts: amlogic: s6: add power domain controller node
dts: arm64: amlogic: Add ISP related nodes for C3
arm64: dts: meson: add initial device-tree for Tanix TX9 Pro
dt-bindings: arm: amlogic: add support for Tanix TX9 Pro
...
Convert the Marvell AP80x System Controller binding to DT schema format.
There's not any specific compatible for the whole block which is a
separate problem, so just the child nodes are documented. Only the
pinctrl and clock child nodes need to be converted as the GPIO node
already has a schema.
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20251014153040.3783896-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Convert the Marvell CP110 System Controller binding to DT schema
format.
There's not any specific compatible for the whole block which is a
separate problem, so just the child nodes are documented. Only the
pinctrl and clock child nodes need to be converted as the GPIO node
already has a schema.
Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20251022165509.3917655-2-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
