Jingyi Wang
58e69e8f9c
dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for Kaanapali
...
Document CPUSS Control Processor (CPUCP) mailbox controller for Qualcomm
Kaanapali, which is compatible with X1E80100, use fallback to indicate
this.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com >
Acked-by: Rob Herring (Arm) <robh@kernel.org >
Link: https://lore.kernel.org/r/20251021-knp-cpufreq-v2-1-95391d66c84e@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2026-01-16 13:31:14 -06:00
Jagadeesh Kona
65ce09d2f1
dt-bindings: mailbox: qcom: Document SM8750 CPUCP mailbox controller
...
Document CPU Control Processor (CPUCP) mailbox controller for Qualcomm
SM8750 SoCs. It is software compatible with X1E80100 CPUCP mailbox
controller hence fallback to it.
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com >
Acked-by: Rob Herring (Arm) <robh@kernel.org >
Link: https://lore.kernel.org/r/20251211-sm8750-cpufreq-v1-1-394609e8d624@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org >
2026-01-03 12:16:36 -06:00
Sibi Sankar
526ce9eb45
dt-bindings: mailbox: qcom: Document Glymur CPUCP mailbox controller binding
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Document CPU Control Processor (CPUCP) mailbox controller for Qualcomm
Glymur SoCs. It is software compatible with X1E80100 CPUCP mailbox
controller hence fallback to it.
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com >
Acked-by: Rob Herring (Arm) <robh@kernel.org >
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com >
2025-10-06 18:13:53 -05:00
Sibi Sankar
6e7c4cc55d
dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings
...
Add devicetree binding for CPUSS Control Processor (CPUCP) mailbox
controller.
Reviewed-by: Rob Herring <robh@kernel.org >
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com >
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com >
2024-07-10 13:24:55 -05:00
