2 Commits

Author	SHA1	Message	Date
Clément Le Goffic	dffaa1beea	dt-bindings: memory: factorise LPDDR props into SDRAM props ... LPDDR and DDR bindings are SDRAM types and are likely to share the same properties (at least for density, io-width and reg). To avoid bindings duplication, factorise the properties. The compatible description has been updated because the MR (Mode registers) used to get manufacturer ID and revision ID are not present in case of DDR. Those information should be in a SPD (Serial Presence Detect) EEPROM in case of DIMM module or are known in case of soldered memory chips as they are in the datasheet of the memory chips. Signed-off-by: Clément Le Goffic <clement.legoffic@foss.st.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Clément Le Goffic <legoffic.clement@gmail.com> Link: https://patch.msgid.link/20251118-b4-ddr-bindings-v9-1-a033ac5144da@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>	2025-12-18 17:09:38 +01:00
Julius Werner	a500528fb3	dt-bindings: memory: Add jedec,lpddr4 and jedec,lpddr5 bindings ... This patch adds bindings for LPDDR4 and LPDDR5 memory analogous to the existing bindings for LPDDR2 and LPDDR3. For now, the new types are only needed for topology description, so other properties like timing parameters are omitted. They can be added later if needed. Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220930220606.303395-3-jwerner@chromium.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>	2022-10-18 13:05:15 -04:00