David Lechner
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2e706f86a5
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spi: dt-bindings: adi,axi-spi-engine: add multi-lane support
Extend the ADI AXI SPI engine binding for multiple data lanes. This SPI
controller has a capability to read multiple data words at the same
time (e.g. for use with simultaneous sampling ADCs). The current FPGA
implementation can support up to 8 data lanes at a time (depending on a
compile-time configuration option).
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20260123-spi-add-multi-bus-support-v6-6-12af183c06eb@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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2026-02-02 12:12:46 +00:00 |
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David Lechner
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e1101373df
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spi: dt-bindings: axi-spi-engine: add SPI offload properties
The AXI SPI Engine has support for hardware offloading capabilities.
This includes a connection to a DMA controller for streaming RX or TX
data and a trigger input for starting execution of the SPI message
programmed in the offload. It is designed to support up to 32 offload
instances.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20250207-dlech-mainline-spi-engine-offload-2-v8-6-e48a489be48c@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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2025-02-07 20:17:12 +00:00 |
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David Lechner
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252eafe11f
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dt-bindings: spi: axi-spi-engine: convert to yaml
This converts the axi-spi-engine binding to yaml.
There are a few minor fixes in the conversion:
* Added maintainers.
* Added descriptions for the clocks.
* Fixed the double "@" in the example.
* Added a comma between the clocks in the example.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20231117-axi-spi-engine-series-1-v1-1-cc59db999b87@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
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2023-11-20 13:29:03 +00:00 |
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