Commit Graph

6 Commits

Author SHA1 Message Date
Conor Dooley
dfb208b9ae clk: microchip: drop POLARFIRE from ARCH_MICROCHIP_POLARFIRE
This driver is used by non-polarfire devices now, and the ARCH_MICROCHIP
symbol has been defined for some time on RISCV so drop it without any
functional change.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20260113-doing-surplus-dc45866f71d4@spud
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2026-01-16 08:48:38 +02:00
Conor Dooley
c6f2dddfa7 clk: microchip: mpfs: use regmap for clocks
Convert the PolarFire SoC clock driver to use regmaps instead of iomem
addresses as a preparatory work for supporting the new binding for this
device that will only provide the second of the two register regions, and
will require the use of syscon regmap to access the "cfg" and "periph"
clocks currently supported by the driver.

This is effectively a revert of commit 4da2404bb0 ("clk: microchip:
mpfs: convert cfg_clk to clk_divider") and commit d815569783 ("clk:
microchip: mpfs: convert periph_clk to clk_gate") as it resurrects the
ops structures removed in those commits, with the readl()s and
writel()s replaced by regmap_read()s and regmap_writes()s.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Link: https://lore.kernel.org/r/20251029-surfboard-refocus-ca9b135ab123@spud
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-11-02 15:22:58 +02:00
Conor Dooley
f3e788d9ec clk: microchip: convert SOC_MICROCHIP_POLARFIRE to ARCH_MICROCHIP_POLARFIRE
As part of converting RISC-V SOC_FOO symbols to ARCH_FOO to match the
use of such symbols on other architectures, convert the Microchip FPGA
clock drivers to use the new symbol.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20230309204452.969574-2-conor@kernel.org
2023-05-22 11:57:27 +03:00
Conor Dooley
3c79ace9c0 clk: microchip: enable the MPFS clk driver by default if SOC_MICROCHIP_POLARFIRE
With the intent of removing driver selects from Kconfig.socs in
arch/riscv, essential drivers that were being selected there could
instead by enabled by defaulting them to the value of the SoC's Kconfig
symbol.

Do so here & drop the depend on RISC-V - the SOC_ symbols are only
defined there anyway.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221123161921.81195-1-conor@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-12-08 17:12:08 -08:00
Conor Dooley
b56bae2dd6 clk: microchip: mpfs: add reset controller
Add a reset controller to PolarFire SoC's clock driver. This reset
controller is registered as an aux device and read/write functions
exported to the drivers namespace so that the reset controller can
access the peripheral device reset register.

Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com
2022-09-14 10:55:17 +03:00
Daire McNamara
635e5e7337 clk: microchip: Add driver for Microchip PolarFire SoC
Add support for clock configuration on Microchip PolarFire SoC

Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Co-developed-by: Padmarao Begari <padmarao.begari@microchip.com>
Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Co-developed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220222121143.3316880-2-conor.dooley@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2022-03-11 19:31:52 -08:00