Commit Graph

20 Commits

Author SHA1 Message Date
Shaoyun Liu
d0c989a0aa drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12_1
Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:59:56 -05:00
Mukul Joshi
5a8c343d2e drm/amdgpu: Cleanup gmc_v12_1 after 6.16 merge
After the 6.16 merge, some changes not applicable to GFX 12.1 were
added in the gmc_v12_1_get_vm_pte function. Additionally, add the
case for MTYPE RW for GFX 12.1.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:59:56 -05:00
Likun Gao
acf07acfae drm/amdgpu: skip gfxhub tlb flush if gfx is power off
Skip for gfxhub tlb flush for gc v12_1 if gfx is not poweron.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:59:55 -05:00
Mukul Joshi
2d70a10dd1 drm/amdgpu: Always set PTE.B for device memory on GFX 12.1
On GFX 12.1, we need to set the atomics bit (PTE.B) always for
device memory.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:59:55 -05:00
Mukul Joshi
382dd7d23d drm/amdgpu: Setup MTYPE on SOC models for GFX 12.1
Fix it to apply for all models.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:27:22 -05:00
Mukul Joshi
b7c4040d0d drm/amdgpu: Use correct MES pipe in non-SPX mode on GFX 12.1
On GFX 12.1, use the correct MES pipe instance for readiness before
sending MES commands on that pipe. Additionally, send the TLB requests
on the correct MES pipe in non-SPX modes.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:26:52 -05:00
Mukul Joshi
44fc86f2a3 drm/amdgpu: Program IH_VMID_LUT_INDEX register on GFX 12.1
For querying VMID <-> PASID mapping on GFX 12.1, we need to first
program the IH_VMID_LUT_INDEX before fetching the LUT mapping. Without
this TLB flush may not work.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Reviewed-by:  Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:26:15 -05:00
Likun Gao
89745c19c6 drm/amdgpu: Correct xcc_id input to GET_INST from physical to logic
Correct xcc_id input to GET_INST from physical to logic for
gfx_v12_1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16 13:28:16 -05:00
Philip Yang
8efa1a11e1 drm/amdgpu: Support 57bit fault address for GFX 12.1.0
The gmc fault virtual address is up to 57bit for 5 level page table,
this also works with 48bit virtual address for 4 level page table.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Acked-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16 13:28:09 -05:00
Hawking Zhang
db9ca58e16 drm/amdgpu: Add soc v1_0 ih client id table
To acommandate the specific ih client for soc v1_0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16 13:27:42 -05:00
Mukul Joshi
0c9ad47286 drm/amdgpu: Flush TLB on all XCCs on GFX 12.1
Currently, the driver code is flushing TLB on XCC 0 only.
Fix it by flushing on all XCCs within the partition.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16 13:27:39 -05:00
Likun Gao
bf2951e967 drm/amdgpu: enable gpu tlb flush for gfxhub
Enable gpu tlb flush for gfxhub without check gfx.is_poweron
as gfx is power on by default for gfx v12_1 ASIC.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16 13:23:14 -05:00
Le Ma
a848986a38 drm/amdgpu: Use AMDGPU_IS_GFXHUB to screen out GFXHUB for GMC v12.1
There're multiple gfxhubs on GMC v12.1

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16 13:23:04 -05:00
Hawking Zhang
e2a6a4e6d4 drm/amdgpu: Initialize vram_info for gmc v12_1
Initialize vram_info for gmc v12_1

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:39:27 -05:00
Hawking Zhang
51b9bb61e5 drm/amdgpu: Initialize memory partition callbacks for gmc v12_1
Initialize memory partition callbacks for gmv v12_1

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:39:19 -05:00
Mukul Joshi
4c5f7d7388 drm/amdgpu: Add interrupt handler for GFX 12.1.0
Add a separate interrupt handler for handling interrupts,
both retry and no-retry, for GFX 12.1.0.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:38:56 -05:00
Mukul Joshi
c93f9b7db8 drm/amdgpu: Setup MTYPEs for GFX 12.1.0
For GFX 12.1.0, setup correct MTYPE for a BO depending on
its current location relative to the mapping GPU.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by:  Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 14:25:54 -05:00
Mukul Joshi
4da4990337 drm/amdgpu: Setup PCIe atomics bit in PTE on GFX 12.1.0
To enable atomic access to memory, setup the new PCIe atomics bit
in PTE on GFX 12.1.0.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 14:13:01 -05:00
Mukul Joshi
b8c27208b2 drm/amdgpu: Always set snoop bit in PDE on GFX 12.1
GFX 12.1 has the requirement to always set snoop bit in PDE
to maintain coherency.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 13:56:35 -05:00
Hawking Zhang
5056b75fed drm/amdgpu: Add gmc v12_1 gmc callbacks
Implement gmc v12_1 gmc callbacks

v2: revert temporary PDE MTYPE to UC setting

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 13:56:35 -05:00