Commit Graph

13 Commits

Author SHA1 Message Date
Shaoyun Liu
d0c989a0aa drm/amd/amdgpu : Use the MES INV_TLBS API for tlb invalidation on gfx12_1
Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com>
Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:59:56 -05:00
Likun Gao
fcc4fc758e drm/amdgpu: make normalize reg addr to common func for soc v1
Normalize registers address to local xcc address for sdma v7_1.
Merge normalize register address function to an common function
for soc v1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:27:24 -05:00
Mukul Joshi
aa0f09f93d drm/amdgpu: Rework MES initialization on GFX 12.1
Currently, only SPX mode works on GFX 12.1. This patch reworks
the MES initialization to get other non-SPX modes working. For example,
for CPX mode, coop_enable bit needs to be set to 0. The shared command
buffer initialization is also not needed in CPX mode.
The shared command buffer initialization needs further improvements which
will be handled in later patches.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:27:00 -05:00
Jack Xiao
b9a0716a93 drm/amdgpu/mes_v12_1: fix mes access xcd register
Fix to use local register offset inside die for mes fw accessing
local/remote xcd register.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16 13:29:01 -05:00
Likun Gao
1eb2a5ed19 drm/amdgpu: use physical xcc id to get rrmt
Use physical xcc_id to get rrmt on misc_op for mes v12_1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16 13:28:50 -05:00
Mukul Joshi
3235a5b723 drm/amdgpu: Update MES VM_CNTX_CNTL for XNACK off for GFX 12.1
Currently, we do not turn off retry faults in VM_CONTEXT_CNTL value
when passing it to MES if XNACK is off. This creates a situation where
XNACK is disabled in SQ but enabled in UTCL2, which is not recommended.
As a result, turn off/on retry faults in both SQ and UTCL2 when passing
vm_context_cntl value to MES if XNACK is disabled/enabled.

Suggested-by: Jay Cornwall <jay.cornwall@amd.com>
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:39:09 -05:00
Mukul Joshi
cc52af1a96 drm/amdkfd: Enable per-process XNACK for GFX 12.1.0
GFX 12.1.0 will support enabling/disabling XNACK on a per-
process basis. This change enables the per process XNACK feature.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:39:06 -05:00
Likun Gao
77385a2dc1 drm/amdgpu: enable unmap doorbell handle for gfx v12_1
Enable unmapped doorbell handling for gfx v12_1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:35:02 -05:00
Likun Gao
a5192fbb2e drm/amdgpu: fix mes code error for muti-xcc
Fix some code error for muti-xcc on mes v12_1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 14:27:17 -05:00
Michael Chen
61a3ade2f6 drm/amdgpu/mes12_1: set multi-xcc mes log address
Set mes event log address based on xcc id and pipe.

Signed-off-by: Michael Chen <michael.chen@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 14:13:20 -05:00
Jack Xiao
75053887d6 drm/amdgpu/mes12_1: add cooperative dispatch support
Add initial cooperative dispatch MES support.
a. set shared cmd buffer for the group of cooperative dispatch mes.
b. automatically dispatch add_hw_queue/remove_hw_queue to master mes.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 14:13:15 -05:00
Alex Sierra
f8692d2f9a drm/amd: include rrmt mode for mes_v12_1
Implement rrmt for misc read/write regs ops in mes_v12.
This covers LOCAL/REMOTE XCD and LOCAL/REMOTE AID.

v2: fix comments (Alex)

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 14:11:56 -05:00
Jack Xiao
e220edf2d6 drm/amdgpu/mes_v12_1: initial support for mes_v12_1
Duplicated and rename mes ip version name to v12_1_0.
Fix to access correct ring pipe by xcc_id.
Fix to access correct instance registers by xcc_id.
Fix to access correct index registers by grbm/xcc_id.

v2: rebase (Alex)
v3: fix sw_fini (Alex)

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Mukul Joshi <mukul.joshi@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 13:56:39 -05:00