Commit Graph

11 Commits

Author SHA1 Message Date
Le Ma
216779827f drm/amdgpu: add helpers to access cross-die registers smn addr for soc v1_0
Encode die_id/socket_id for upper 32bits of soc v1_0 registers SMN address.

v2: fix logical error caught by clang

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:59:57 -05:00
Likun Gao
87046288e8 drm/amdgpu: set aid_mask for soc v1
Set aid_mask via xcc_mask.

v2: squash in follow up change

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:59:57 -05:00
Likun Gao
60481d95ad drm/amdgpu: update mcm_addr_lut data for imu v12_1
Support for partition mode to program MCM_ADDR_LUT.

v2: clean up (Alex)

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:59:55 -05:00
Likun Gao
fcc4fc758e drm/amdgpu: make normalize reg addr to common func for soc v1
Normalize registers address to local xcc address for sdma v7_1.
Merge normalize register address function to an common function
for soc v1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:27:24 -05:00
Mukul Joshi
fd25254f0b drm/amdgpu: Report correct compute partition mode on GFX 12.1
PSP programs the NBIO partition status register. In the absence of PSP,
read the current compute partition from the GFX IMU register instead of
NBIO.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:27:17 -05:00
Hawking Zhang
9987a6f34e drm/amdgpu: Init partition_mode and xcc_mask for GFX_IMU_PARTITION_SWITCH
Set partition_mode and physical xcc mask fields in
GFX_IMU_PARTITION_SWITCH register

v2: cleanup (Alex)

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:39:29 -05:00
Likun Gao
d6e8148328 drm/amdgpu: update sdma configuration for soc v1_0
Update SDMA instances/masks according to xcc num for
multi-xcc models on soc v1.0.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:38:10 -05:00
Hawking Zhang
f9ed1d463e drm/amdgpu: Initialize xcp manager for soc v1_0
Initialize xcp manager for soc v1_0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:38:07 -05:00
Hawking Zhang
a936896135 drm/amdgpu: Add soc_v1_0_xcp_funcs
Implement xcp mgr callbacks for soc v1_0

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10 17:38:05 -05:00
Likun Gao
fe1c48e9bd drm/amdgpu: add soc config init for GC v12_1
Add function to initialize soc configuration information
for GC 12.1.0 ASICs.
Use it to map IPs and other SOC related information once IP
configuration information is available through discovery.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 14:13:37 -05:00
Hawking Zhang
297b0cebbc drm/amdgpu: Add soc v1_0 support
v1_0 is a new generation ip block

v2: squash in doorbell changes (Alex)
v3: squash in xclk, reset placeholders, pcie r|wreg ext callbacks

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 13:56:38 -05:00