Commit Graph

4 Commits

Author SHA1 Message Date
Le Ma
216779827f drm/amdgpu: add helpers to access cross-die registers smn addr for soc v1_0
Encode die_id/socket_id for upper 32bits of soc v1_0 registers SMN address.

v2: fix logical error caught by clang

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:59:57 -05:00
Likun Gao
fcc4fc758e drm/amdgpu: make normalize reg addr to common func for soc v1
Normalize registers address to local xcc address for sdma v7_1.
Merge normalize register address function to an common function
for soc v1.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-01-05 16:27:24 -05:00
Likun Gao
fe1c48e9bd drm/amdgpu: add soc config init for GC v12_1
Add function to initialize soc configuration information
for GC 12.1.0 ASICs.
Use it to map IPs and other SOC related information once IP
configuration information is available through discovery.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 14:13:37 -05:00
Hawking Zhang
297b0cebbc drm/amdgpu: Add soc v1_0 support
v1_0 is a new generation ip block

v2: squash in doorbell changes (Alex)
v3: squash in xclk, reset placeholders, pcie r|wreg ext callbacks

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08 13:56:38 -05:00