Clay King
bdbb6a14db
drm/amd/display: Array offset used before range check
...
Consolidating multiple CodeQL Fixes for alerts with rule id: cpp/offset-use-before-range-check
Reviewed-by: Joshua Aberback <joshua.aberback@amd.com >
Signed-off-by: Clay King <clayking@amd.com >
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com >
Tested-by: Dan Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2025-08-27 13:57:50 -04:00
Hersen Wu
188fd1616e
drm/amd/display: Fix index may exceed array range within fpu_update_bw_bounding_box
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[Why]
Coverity reports OVERRUN warning. soc.num_states could
be 40. But array range of bw_params->clk_table.entries is 8.
[How]
Assert if soc.num_states greater than 8.
Reviewed-by: Alex Hung <alex.hung@amd.com >
Acked-by: Tom Chung <chiahsuan.chung@amd.com >
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-05-02 16:18:18 -04:00
Alvin Lee
f0ec30549a
drm/amd/display: Ensure populate uclk in bb construction
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[Description]
- For some SKUs, the optimal DCFCLK for each UCLK is less than the
smallest DCFCLK STA target due to low memory bandwidth. There is
an assumption that the DCFCLK STA targets will always be less
than one of the optimal DCFCLK values, but this is not true for
SKUs that have low memory bandwidth. In this case we need to
populate the optimal UCLK for each DCFCLK STA targets as the max
UCLK freq.
- Also fix a bug in DML where start_state is not assigned and used
correctly.
Reviewed-by: Samson Tam <samson.tam@amd.com >
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com >
Acked-by: Alex Hung <alex.hung@amd.com >
Signed-off-by: Alvin Lee <alvin.lee2@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2024-01-15 18:35:39 -05:00
Jiapeng Chong
1be3188a6d
drm/amd/display: Clean up some inconsistent indenting
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No functional modification involved.
smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:205 dcn303_fpu_update_bw_bounding_box() warn: inconsistent indenting.
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:355 dcn303_fpu_init_soc_bounding_box() warn: inconsistent indenting.
Reported-by: Abaci Robot <abaci@linux.alibaba.com >
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-07-28 16:05:16 -04:00
Jasdeep Dhillon
53923e62af
drm/amd/display: move FPU associated DCN303 code to DML folder
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[Why & How]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/ , isolate
code that uses FPU in DCN303 to DML, where all FPU code
should locate.
Co-authored-by: Jasdeep Dhillon <jasdeep.dhillon@amd.com >
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com >
Acked-by: Alan Liu <HaoPing.Liu@amd.com >
Signed-off-by: Jasdeep Dhillon <jasdeep.dhillon@amd.com >
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com >
Signed-off-by: Alex Deucher <alexander.deucher@amd.com >
2022-03-15 14:25:15 -04:00
