Commit Graph

13 Commits

Author SHA1 Message Date
Nemesa Garg
82860cba5f drm/i915/display: Add and compute scaler parameter
Compute the values for second scaler for sharpness.
Fill the register bits corresponding to the scaler.

v1: Rename the title of patch [Ankit]
v2: Remove setup_casf from here[Ankit]
v3: Add skl_scaler_setup_casf in casf_enable

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251028120747.3027332-7-ankit.k.nautiyal@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-10-30 15:43:24 +02:00
Ville Syrjälä
9704c1cbed drm/i915/wm: Add WM0 prefill helpers
Add skl_wm0_prefill_lines() (based on the actual state) and
skl_wm0_prefill_lines_worst() (worst case estimate) which
tell us how many extra lines are needed in prefill for WM0.

The returned numbers are in .16 binary fixed point.

TODO: skl_wm0_prefill_lines_worst() is a bit rough still

v2: Drop all pre-icl FIXMEs since this only gets used for VRR guardband

Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251014191808.12326-8-ville.syrjala@linux.intel.com
2025-10-16 18:21:48 +03:00
Ville Syrjälä
b95e31cdfc drm/i915/scaler: Add scaler prefill helpers
Add helpers to compute the required prefill line count and
adjustment factors for the scalers.

The "1st" variants hand out numbers for the first scaler stage
in the pipeline (pipe scaler if no plane scalers are enabled,
or the max from all the plane scaler). The "2nd" variants deal
with second scaler stage (pipe scaler when plane scaling is also
enabled, otherwise there is no second stage).

The _worst() variants give out worst case estimates, meant for
guardband sizing. The other variants are meant for the actual
vblank/guardband length check vs. prefill+pkgc/sagv latency.

The returned numbers are in .16 binary fixed point.

TODO: pretty rough, should check the actual scaler max scaling
      factors instead of just assuming 3x everywhere
TODO: Reorder scaler assignment vs. vblank length check to get
      the actual scale factors

v2: Drop debugs
v3: Ignore scale factors for the vblank length check for now
    since we don't have the scalers assigned yet

Reviewed-by: Uma Shankar <uma.shankar@intel.com> #v1
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20251015125645.11230-1-ville.syrjala@linux.intel.com
2025-10-16 18:21:24 +03:00
Nemesa Garg
73309ed9d5 drm/i915/display: WA_14011503117
Mask the ERR_FATAL_MASK before scaler initialization.
After enabling the scaler and waiting for one frame,
unmask the previously masked bits, PS_ECC and
ERR_FATAL_MASK
Unmasking of ERR_FATAL_MASK bit is use for
validation purpose. There is no functional
impact.

v2: Remove intel_display_need_wa[Jani]
    Optimize the ecc_unmask call[Animesh]
v3: Add intel_display_wa[Jani]

Signed-off-by: Nemesa Garg <nemesa.garg@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250801125835.2337614-1-nemesa.garg@intel.com
2025-08-05 17:25:32 +05:30
Jani Nikula
b116bd3ad3 drm/i915/display: remove superfluous <linux/types.h> includes
Commit f7a9dc7965 ("drm/i915/scaler: Use intel_display as argument to
skl_scaler_max_src_size") added superfluous includes. Remove them.

Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20250728102113.238730-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
2025-07-29 11:20:43 +03:00
Suraj Kandpal
3347b55f2c drm/i915/xe3lpd: Prune modes for YUV420
We only support resolution up to 4k for single pipe when using
YUV420 format so we prune these modes and restrict the plane size
at src. This is because pipe scaling will not support YUV420 scaling
for hwidth > 4096.

--v2
-Use output format to check [Ville]
-Add Bspec references
-Modify commit messge to point to why this is needed

--v3
-Use a function skl_scaler_mode_valid which is routed throug
intel_pfit_mode_valid [Ville]
-Combine the check conditons [Jonathan]

--v4
-mode_valid functions should return drm_mode_status [Jani]

--v5
-Use skl_scaler_max_src_size [Ankit]

Bspec: 49247, 50441
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com> #v2
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250708043328.1086192-2-suraj.kandpal@intel.com
2025-07-11 09:38:31 +05:30
Ville Syrjälä
b4ebc06212 drm/i915/dsb: Plumb dsb into plane scaler functions
We want to start doing scaler programming (plane scalers
only initially) on the DSB. To that end plumb the DSB into
the relevant places in the scaler code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250218205850.1422-3-ville.syrjala@linux.intel.com
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
2025-02-27 22:44:49 +02:00
Ville Syrjälä
b5b4b53883 drm/i915/scaler: Pass the whole atomic state into intel_atomic_setup_scalers()
intel_atomic_setup_scalers() currently digs out the full atomic
state from the crtc state. Flip that on its head so that we instead
pass in the full atomic state and dig out the crtc state (and whatever
else we need). This is generallte the better approach as it works
in all phases of the atomic commit, whereas the other apporoach only
really works during .atomic_check().

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241107122658.21901-4-ville.syrjala@linux.intel.com
2024-11-12 00:06:59 +02:00
Ville Syrjälä
e912069e61 drm/i915/scaler: Remove redudant junk from skl_scaler.h
Nuke some redundant includes and forward declarations from
skl_scaler.h.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241107122658.21901-3-ville.syrjala@linux.intel.com
2024-11-12 00:06:54 +02:00
Ville Syrjälä
7488f64e89 drm/i915/scaler: s/intel_crtc/crtc/ etc.
Rename some variables from the intel_foo to just foo, to match
the more modern style used throughout the driver.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241107122658.21901-2-ville.syrjala@linux.intel.com
2024-11-12 00:06:49 +02:00
Ville Syrjälä
597421a806 drm/i915: Relocate skl_get_pfit_config()
Move skl_get_pfit_config() next to the other skl+ scaler code
and rename it to skl_scaler_get_config() so that it has a consistnet
namespace.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230418175528.13117-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-04-20 15:14:33 +03:00
Ville Syrjälä
8976b18249 drm/i915: Relocate intel_atomic_setup_scalers()
Move intel_atomic_setup_scalers() next to the other scaler
code in skl_scaler.c.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230418175528.13117-4-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
2023-04-20 15:14:17 +03:00
Dave Airlie
714b1cdb02 drm/i915: refactor skylake scaler code into new file.
This moves the code from various places and consolidates it
into one new file.

v2:
- rename skl_program_plane -> skl_program_plane_scaler (Ville)
- also move skl_pfit_enable, and consequently make some skl_scaler_*
  functions static to skl_scaler.c (Ville)

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/2fa703ffc7b96a41c392fd5ebbd2e6e4ffb6fb05.1612536383.git.jani.nikula@intel.com
2021-02-08 12:12:41 +02:00