Commit Graph

9 Commits

Author SHA1 Message Date
Ben Skeggs
ca79e49d6a drm/nouveau/gr/gf100-: fix race condition in fecs/gpccs ucode
This is a simplied version of the fix by Roy in fdo#93629.  While this
doesn't appear to fix the issues for the users in that report, it's a
real issue that deserves to be resolved.

Reported-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-05-20 14:43:04 +10:00
Roy Spliet
786656295b drm/nouveau/gr/fuc: Store $r0 in interrupt handler
It's supposed to always be 0, but at least nv_iowr() temporarily violates
this. Since the ih touches $r0, it should be stored.

Signed-off-by: Roy Spliet <rs855@cam.ac.uk>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-03-14 10:13:37 +10:00
Ben Skeggs
21f560e990 drm/nouveau/gr/gm107-: make use of gpc_addr() macro for tpc ramchain setup
Should be no functional change here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2016-01-11 11:17:40 +10:00
Ben Skeggs
ccb7b6ba07 drm/nouveau/gr/gf117-: read NV_PGRAPH_GPC_GPM_PD_PES_TPC_ID_MASK from correct GPC
Each GPCCS unit was reading the mask from GPC0, which causes problems on
boards where some GPCs are missing PPCs.

Part of the fix for fdo#92761.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25 15:31:21 +10:00
Ben Skeggs
7028156a91 drm/nouveau/gr/gf100-: split out per-gpc address calculation macro
There's a few places where we need to access a GPC register from ucode,
but outside of the falcon's io address space.  To do this we need to
calculate the offset based on which GPC we're executing on.

This used to be done manually, but we've since found a "base" offset
that can be added by the hardware.  To use this, an extra bit needs to
be set in the register address, which is what this macro achieves.

There should be no functional change from this commit.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-11-25 15:31:21 +10:00
Ben Skeggs
8fd4b7d438 drm/nouveau/gr/gm107: support tpc "strand" ctxsw in gpccs ucode
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-04-14 17:00:53 +10:00
Ben Skeggs
2a19b3ed65 drm/nouveau/gr/gf100-: support mmio access with gpc offset from gpccs ucode
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-04-14 17:00:53 +10:00
Ben Skeggs
e3c71eb274 drm/nouveau/gr: namespace + nvidia gpu names (no binary change)
The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-22 12:18:02 +10:00
Ben Skeggs
b8bf04e1fd drm/nouveau/gr: rename from graph (no binary change)
Shorter device name, match Tegra and our existing enums.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-01-22 12:17:45 +10:00