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472 Commits

Author SHA1 Message Date
Tony Cheng
68199bd16c drm/amd/display: Move address tracking out of HUBP 
[Why]
We sometime require remapping of FB address space to UMA

[How]
Move address tracking up a layer before we apply address translation

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-16 16:11:50 -05:00
Gloria Li
bf53769d9f drm/amd/display: add HDR visual confirm 
[Why]
Testing team wants a way to tell if HDR is on or not

[How]
Program the overscan color to visually indicate the HDR state of the top-most plane

Signed-off-by: Gloria Li <geling.li@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-16 16:11:49 -05:00
Krunoslav Kovac
6d92b5c2d5 drm/amd/display: Refactor SDR cursor boosting in HDR mode 
[Why]
Cursor boosting is done via CNVC_CUR register which is DPP, not HUBP
Previous commit was implementing it in HUBP functions,
and also breaking diags tests.

[How]
1. Undo original commit as well as Eric's diags test fix, almost completely
2. Move programming to DPP and call via new dc_stream function
3. Also removing cur_rom_en from dpp_cursor_attributes and programming
as part of normal cursor attributes as it depends on cursor color format

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-16 16:11:49 -05:00
Dmytro Laktyushkin
ec95213112 drm/amd/display: properly turn autocal off 
[why]
Currently we do not turn off autocal when scaling is in bypass.
In case vbios enalbes auto scale and our first mode set is a non-scaled
mode we have autocal on causing screen corruption.

[how]
moves turning autocal off to be first thing done during scaler setup

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:52:33 -05:00
Hugo Hu
522e6b434a drm/amd/display: Initialize data structure for DalMpVisualConfirm. 
[Why] Prevent unexpected color shows if DalMpVisualConfirm enable.
[How] Zero out color configuration data for DalMpVisualConfirm when initiating.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:52:25 -05:00
David Francis
aca3e9a49b drm/amd/display: Expose couple OPTC functions through header 
Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:51:47 -05:00
David Francis
99a100ae32 drm/amd/display: Add CRC support for DCN 
[Why]
Regamma/CTM tests require CRC support

[How]
The CRC registers that were used in DCE exist under different
names in DCN.  The code was copied from DCE (in
dc/dce110/dce110_timing_generator.c) into DCN, and changed to
use the DCN register access helper functions.

Signed-off-by: David Francis <David.Francis@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:51:39 -05:00
Charlene Liu
8fc0a0d4a0 drm/amd/display: add DalEnableHDMI20 key support 
[why]
"DalEnableHDMI20" set to 0, disallow HDMI YCbCr420 and  pixel clock > 340Mhz
Default is enabled.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:51:11 -05:00
Eric Bernstein
c2437b1f16 drm/amd/display: Expose bunch of functions from dcn10_hw_sequencer 
v2: Remove spurious newline changes

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:50:40 -05:00
Yongqiang Sun
ac99243c8d drm/amd/display: expose dcn10_aux_initialize in header 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:50:10 -05:00
Dmytro Laktyushkin
08ed681c84 drm/amd/display: add dcn cursor hotsport rotation and mirror support 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:50:05 -05:00
Dmytro Laktyushkin
39a9f4d89e drm/amd/display: add additional info for cursor position programming 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:49:23 -05:00
Tony Cheng
1bd493e378 drm/amd/display: Expose configure_encoder for link_encoder 
Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:48:16 -05:00
Charlene Liu
8e8539c2fc drm/amd/display: Define couple extra DCN registers 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:48:10 -05:00
Krunoslav Kovac
1811a51f6a drm/amd/display: Implement cursor multiplier 
DCN allows cursor multiplier when blending FP16 surface.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:47:07 -05:00
Eric Bernstein
a9962fb8e5 drm/amd/display: Separate HUBP surface size and rotation/mirror programming 
Separate HUBP surface size and rotation/mirror programming so that
HUBP revision without mirror/rotation do not access those register
fields.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-13 14:46:47 -05:00
Harry Wentland
bd4e725084 drm/amd/display: Make function pointer structs const 
const to avoid hard-to-find bugs where some function overrides a
function pointer.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-10 14:17:23 -05:00
Harry Wentland
25177e7f94 Revert "drm/amd/display: Fix indentation in dcn10 resource constructor" 
That change was a merge gone bad.

This reverts commit cb1d7eacb5.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:40:02 -05:00
Charlene Liu
7f93c1de64 drm/amd/display: add valid regoffset and NULL pointer check 
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:44 -05:00
Yongqiang Sun
b6c3053a8f drm/amd/display: Check scaling ration not viewports params. 
In case of roation, width and height in viewport is difference
between viewport and h_active and v_active, while this is not scaling.
The right way is check ratios in scaling data,
to determine it is a scaling case or not.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:43 -05:00
Dmytro Laktyushkin
e21db6dbdf drm/amd/display: move dcn watermark programming to set_bandwidth 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:43 -05:00
Dmytro Laktyushkin
7144d3cfff drm/amd/display: separate out wm change request dcn workaround 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:42 -05:00
Dmytro Laktyushkin
746c58ed22 drm/amd/display: move dml defaults to respective dcn resource files 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:41 -05:00
Mikita Lipski
5094ffac6b drm/amd/display: Enable PPLib calls from DC on linux 
Set the powerplay debug flag to false for both Windows and Linux
to allow the calls to pplib. So we can retrieve the clock values
from powerplay instead of using default hardcoded values.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:40 -05:00
Dmytro Laktyushkin
b9c1c67aeb drm/amd/display: clean rq/dlg/ttu reg structs before calculations 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:39 -05:00
Zheng, XueLai(Eric)
836758ffe7 drm/amd/display: support ACrYCb2101010 
Signed-off-by: XueLai(Eric), Zheng <XueLai.Zheng@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:37 -05:00
Dmytro Laktyushkin
d7b539d34a drm/amd/display: add safe_to_lower support to dcn wm programming 
This will prevent watermarks from lowering when unsafe to do so.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:36 -05:00
Charlene Liu
7e17cb4ba9 drm/amd/display: Define dp_alt_mode 
Also cleanup command_table2.c. No need for a lot of forward
declarations.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:35 -05:00
Wesley Chalmers
0eebf8ca18 drm/amd/display: Temporarily remove Chroma logs 
To ensure tests continue to pass

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Shahin Khayyer <Shahin.Khayyer@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:34 -05:00
Dmytro Laktyushkin
c910a717da drm/amd/display: clean up set_bandwidth usage 
This removes redundant set_bandwidth calls as well
as fixes a bug in post_set_address_update where dcn1
would never get to lower clocks.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:33 -05:00
Dmytro Laktyushkin
12c3130dd6 drm/amd/display: move dcn1 dispclk programming to dccg 
No functional change.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:32 -05:00
Dmytro Laktyushkin
d578839ca0 drm/amd/display: get rid of cur_clks from dcn_bw_output 
Cleans up dcn_bw_output to only contain calculated info,
actual programmed values will now be stored in respective blocks.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:32 -05:00
Yongqiang Sun
0d8be24134 drm/amd/display: Use tg count for opp init. 
In case of tg count not equal to FE pipe count, if use pipe count to iterate
the tgs, it will cause BSOD.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:31 -05:00
Dmytro Laktyushkin
e2e0a1dcd3 drm/amd/display: move clock programming from set_bandwidth to dccg 
This change moves dcn clock programming(with exception of dispclk)
into dccg. This should have no functional effect.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:28 -05:00
Dmytro Laktyushkin
6ca1124618 drm/amd/display: rename display clock block to dccg 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:28 -05:00
Dmytro Laktyushkin
fab55d61b9 drm/amd/display: redesign dce/dcn clock voltage update request 
The goal of this change is to move clock programming and voltage
requests to a single function. As of this change only dce is affected.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-07-05 16:38:28 -05:00
Eric Bernstein
e9522309ef drm/amd/display: Add num_opp to resource_caps 
Number of OPPs to be instantiated is based on number
of timing generators, not number of pipes.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:24:57 -05:00
Eric Bernstein
12036586a3 drm/amd/display: Allow DP register double buffer 
Remove setting DP_DB_DISABLE to avoid issues when changing
bit depth after vbios take over.
Refactor code to perform single register update for both
pixel encoding and component depth fields.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:24:50 -05:00
Krunoslav Kovac
b73552323a drm/amd/display: Convert quotes to Ascii quotes 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:24:21 -05:00
Eric Bernstein
b4f84bdf57 drm/amd/display: Stream encoder update 
Update stream encoder based on feedback from HW team.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:23:30 -05:00
Eric Bernstein
0b126112e9 drm/amd/display: DP YCbCr 4:2:0 support 
Update MSA MISC1 bit 6 programming to handle YCbCr 4:2:0
and BT2020 cases.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:27 -05:00
Anthony Koo
1a05873f21 drm/amd/display: Refactor audio programming 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:26 -05:00
Hersen Wu
cb1d7eacb5 drm/amd/display: Fix indentation in dcn10 resource constructor 
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:24 -05:00
Eric Bernstein
0f6ca3bac4 drm/amd/display: Add function to get optc active size 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:24 -05:00
Eric Bernstein
ea4a202053 drm/amd/display: pass pipe_ctx straight to blank_pixel_data 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-06-15 12:20:21 -05:00
Dmytro Laktyushkin
0b19fdc45f drm/amd/display: fix dscl_manual_ratio_init 
This change will fix wb and display scaling when ratios of
4 or more are involved

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-29 13:28:29 -05:00
Eric Bernstein
aa6d4a59d6 drm/amd/display: Set TMZ and DCC for secondary surface 
Add register programming to support TMZ and DCC on
secondary surfaces.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-29 13:26:40 -05:00
Eric Bernstein
01884c02c4 drm/amd/display: DP component depth 16 bpc 
Add register programming to support 16bpc component
depth for DP.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-29 13:25:15 -05:00
Eric Bernstein
f0cd0a346d drm/amd/display: DCN1 link encoder 
Create DCN1 link encoder files and update AUX and HPD register access.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-18 16:08:29 -05:00
Nikola Cornij
a944744ba5 drm/amd/display: Clear underflow status for debug purposes 
We want to keep underflow sticky bit on for the longevity tests outside
of test environment. For debug purposes it is, however, useful to clear
underflow status after the test that caused it so that the following
tests are not affected. This change fullfils both requirements by clearing
the underflow only from within Windows or Diags test environment.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-18 16:08:29 -05:00