# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- $id: http://devicetree.org/schemas/dma/xilinx/xlnx,axi-dma.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx AXI VDMA, DMA, CDMA and MCDMA IP maintainers: - Radhey Shyam Pandey - Abin Joseph description: > Xilinx AXI VDMA engine, it does transfers between memory and video devices. It can be configured to have one channel or two channels. If configured as two channels, one is to transmit to the video device and another is to receive from the video device. Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream target devices. It can be configured to have one channel or two channels. If configured as two channels, one is to transmit to the device and another is to receive from the device. Xilinx AXI CDMA engine, it does transfers between memory-mapped source address and a memory-mapped destination address. Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream target devices. It can be configured to have up to 16 independent transmit and receive channels. properties: compatible: enum: - xlnx,axi-cdma-1.00.a - xlnx,axi-dma-1.00.a - xlnx,axi-mcdma-1.00.a - xlnx,axi-vdma-1.00.a reg: maxItems: 1 "#dma-cells": const: 1 "#address-cells": const: 1 "#size-cells": const: 1 interrupts: items: - description: Interrupt for single channel (MM2S or S2MM) - description: Interrupt for dual channel configuration minItems: 1 description: Interrupt lines for the DMA controller. Only used when xlnx,axistream-connected is present (DMA connected to AXI Stream IP). When child dma-channel nodes are present, interrupts are specified in the child nodes instead. clocks: minItems: 1 maxItems: 5 clock-names: minItems: 1 maxItems: 5 dma-ranges: true xlnx,addrwidth: $ref: /schemas/types.yaml#/definitions/uint32 enum: [32, 64] description: The DMA addressing size in bits. xlnx,num-fstores: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 1 maximum: 32 description: Should be the number of framebuffers as configured in h/w. xlnx,flush-fsync: type: boolean description: Tells which channel to Flush on Frame sync. xlnx,sg-length-width: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 8 maximum: 26 default: 23 description: Width in bits of the length register as configured in hardware. xlnx,irq-delay: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 0 maximum: 255 description: Tells the interrupt delay timeout value. Valid range is from 0-255. Setting this value to zero disables the delay timer interrupt. 1 timeout interval = 125 * clock period of SG clock. xlnx,axistream-connected: type: boolean description: Tells whether DMA is connected to AXI stream IP. patternProperties: "^dma-channel(-mm2s|-s2mm)?$": type: object description: Should have at least one channel and can have up to two channels per device. This node specifies the properties of each DMA channel. properties: compatible: enum: - xlnx,axi-vdma-mm2s-channel - xlnx,axi-vdma-s2mm-channel - xlnx,axi-cdma-channel - xlnx,axi-dma-mm2s-channel - xlnx,axi-dma-s2mm-channel interrupts: maxItems: 1 xlnx,datawidth: $ref: /schemas/types.yaml#/definitions/uint32 enum: [32, 64, 128, 256, 512, 1024] description: Should contain the stream data width, take values {32,64...1024}. xlnx,include-dre: type: boolean description: Tells hardware is configured for Data Realignment Engine. xlnx,genlock-mode: type: boolean description: Tells Genlock synchronization is enabled/disabled in hardware. xlnx,enable-vert-flip: type: boolean description: Tells vertical flip is enabled/disabled in hardware(S2MM path). dma-channels: $ref: /schemas/types.yaml#/definitions/uint32 description: Number of dma channels in child node. required: - compatible - interrupts - xlnx,datawidth additionalProperties: false allOf: - $ref: ../dma-controller.yaml# - if: properties: compatible: contains: const: xlnx,axi-vdma-1.00.a then: properties: clock-names: items: - const: s_axi_lite_aclk - const: m_axi_mm2s_aclk - const: m_axi_s2mm_aclk - const: m_axis_mm2s_aclk - const: s_axis_s2mm_aclk minItems: 1 interrupts: false patternProperties: "^dma-channel(-mm2s|-s2mm)?$": properties: compatible: enum: - xlnx,axi-vdma-mm2s-channel - xlnx,axi-vdma-s2mm-channel required: - xlnx,num-fstores - if: properties: compatible: contains: const: xlnx,axi-cdma-1.00.a then: properties: clock-names: items: - const: s_axi_lite_aclk - const: m_axi_aclk interrupts: false patternProperties: "^dma-channel(-mm2s|-s2mm)?$": properties: compatible: enum: - xlnx,axi-cdma-channel - if: properties: compatible: contains: enum: - xlnx,axi-dma-1.00.a - xlnx,axi-mcdma-1.00.a then: properties: clock-names: items: - const: s_axi_lite_aclk - const: m_axi_mm2s_aclk - const: m_axi_s2mm_aclk - const: m_axi_sg_aclk minItems: 1 patternProperties: "^dma-channel(-mm2s|-s2mm)?(@[0-9a-f]+)?$": properties: compatible: enum: - xlnx,axi-dma-mm2s-channel - xlnx,axi-dma-s2mm-channel required: - "#dma-cells" - reg - xlnx,addrwidth - dma-ranges - clocks - clock-names unevaluatedProperties: false examples: - | #include dma-controller@40030000 { compatible = "xlnx,axi-vdma-1.00.a"; reg = <0x40030000 0x10000>; #dma-cells = <1>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x0 0x0 0x40000000>; clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; xlnx,num-fstores = <8>; xlnx,flush-fsync; xlnx,addrwidth = <32>; dma-channel-mm2s { compatible = "xlnx,axi-vdma-mm2s-channel"; interrupts = ; xlnx,datawidth = <64>; }; dma-channel-s2mm { compatible = "xlnx,axi-vdma-s2mm-channel"; interrupts = ; xlnx,datawidth = <64>; }; }; - | #include dma-controller@a4030000 { compatible = "xlnx,axi-dma-1.00.a"; reg = <0xa4030000 0x10000>; #dma-cells = <1>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x0 0x0 0x40000000>; clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>; clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk"; xlnx,addrwidth = <32>; xlnx,sg-length-width = <14>; dma-channel-mm2s { compatible = "xlnx,axi-dma-mm2s-channel"; interrupts = ; xlnx,datawidth = <64>; xlnx,include-dre; }; dma-channel-s2mm { compatible = "xlnx,axi-dma-s2mm-channel"; interrupts = ; xlnx,datawidth = <64>; xlnx,include-dre; }; };