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* kvm-arm64/vgic-v5-ppi: (40 commits) : . : Add initial GICv5 support for KVM guests, only adding PPI support : for the time being. Patches courtesy of Sascha Bischoff. : : From the cover letter: : : "This is v7 of the patch series to add the virtual GICv5 [1] device : (vgic_v5). Only PPIs are supported by this initial series, and the : vgic_v5 implementation is restricted to the CPU interface, : only. Further patch series are to follow in due course, and will add : support for SPIs, LPIs, the GICv5 IRS, and the GICv5 ITS." : . KVM: arm64: selftests: Add no-vgic-v5 selftest KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI Documentation: KVM: Introduce documentation for VGICv5 KVM: arm64: gic-v5: Probe for GICv5 device KVM: arm64: gic-v5: Set ICH_VCTLR_EL2.En on boot KVM: arm64: gic-v5: Introduce kvm_arm_vgic_v5_ops and register them KVM: arm64: gic-v5: Hide FEAT_GCIE from NV GICv5 guests KVM: arm64: gic: Hide GICv5 for protected guests KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5 KVM: arm64: gic-v5: Enlighten arch timer for GICv5 irqchip/gic-v5: Introduce minimal irq_set_type() for PPIs KVM: arm64: gic-v5: Initialise ID and priority bits when resetting vcpu KVM: arm64: gic-v5: Create and initialise vgic_v5 KVM: arm64: gic-v5: Support GICv5 interrupts with KVM_IRQ_LINE KVM: arm64: gic-v5: Implement direct injection of PPIs KVM: arm64: Introduce set_direct_injection irq_op KVM: arm64: gic-v5: Trap and mask guest ICC_PPI_ENABLERx_EL1 writes KVM: arm64: gic-v5: Check for pending PPIs KVM: arm64: gic-v5: Clear TWI if single task running ... Signed-off-by: Marc Zyngier <maz@kernel.org>
162 lines
5.7 KiB
C
162 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ARM64_KVM_HYP_H__
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#define __ARM64_KVM_HYP_H__
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#include <linux/compiler.h>
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#include <linux/kvm_host.h>
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#include <asm/alternative.h>
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#include <asm/sysreg.h>
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DECLARE_PER_CPU(struct kvm_cpu_context, kvm_hyp_ctxt);
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DECLARE_PER_CPU(unsigned long, kvm_hyp_vector);
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DECLARE_PER_CPU(struct kvm_nvhe_init_params, kvm_init_params);
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/*
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* Unified accessors for registers that have a different encoding
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* between VHE and non-VHE. They must be specified without their "ELx"
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* encoding, but with the SYS_ prefix, as defined in asm/sysreg.h.
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*/
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#if defined(__KVM_VHE_HYPERVISOR__)
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#define read_sysreg_el0(r) read_sysreg_s(r##_EL02)
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#define write_sysreg_el0(v,r) write_sysreg_s(v, r##_EL02)
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#define read_sysreg_el1(r) read_sysreg_s(r##_EL12)
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#define write_sysreg_el1(v,r) write_sysreg_s(v, r##_EL12)
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#define read_sysreg_el2(r) read_sysreg_s(r##_EL1)
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#define write_sysreg_el2(v,r) write_sysreg_s(v, r##_EL1)
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#else // !__KVM_VHE_HYPERVISOR__
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#if defined(__KVM_NVHE_HYPERVISOR__)
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#define VHE_ALT_KEY ARM64_KVM_HVHE
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#else
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#define VHE_ALT_KEY ARM64_HAS_VIRT_HOST_EXTN
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#endif
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#define read_sysreg_elx(r,nvh,vh) \
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({ \
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u64 reg; \
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asm volatile(ALTERNATIVE(__mrs_s("%0", r##nvh), \
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__mrs_s("%0", r##vh), \
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VHE_ALT_KEY) \
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: "=r" (reg)); \
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reg; \
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})
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#define write_sysreg_elx(v,r,nvh,vh) \
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do { \
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u64 __val = (u64)(v); \
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asm volatile(ALTERNATIVE(__msr_s(r##nvh, "%x0"), \
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__msr_s(r##vh, "%x0"), \
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VHE_ALT_KEY) \
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: : "rZ" (__val)); \
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} while (0)
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#define read_sysreg_el0(r) read_sysreg_elx(r, _EL0, _EL02)
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#define write_sysreg_el0(v,r) write_sysreg_elx(v, r, _EL0, _EL02)
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#define read_sysreg_el1(r) read_sysreg_elx(r, _EL1, _EL12)
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#define write_sysreg_el1(v,r) write_sysreg_elx(v, r, _EL1, _EL12)
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#define read_sysreg_el2(r) read_sysreg_elx(r, _EL2, _EL1)
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#define write_sysreg_el2(v,r) write_sysreg_elx(v, r, _EL2, _EL1)
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#endif // __KVM_VHE_HYPERVISOR__
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/*
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* Without an __arch_swab32(), we fall back to ___constant_swab32(), but the
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* static inline can allow the compiler to out-of-line this. KVM always wants
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* the macro version as it's always inlined.
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*/
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#define __kvm_swab32(x) ___constant_swab32(x)
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int __vgic_v2_perform_cpuif_access(struct kvm_vcpu *vcpu);
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u64 __gic_v3_get_lr(unsigned int lr);
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void __gic_v3_set_lr(u64 val, int lr);
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void __vgic_v3_save_state(struct vgic_v3_cpu_if *cpu_if);
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void __vgic_v3_restore_state(struct vgic_v3_cpu_if *cpu_if);
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void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *cpu_if);
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void __vgic_v3_deactivate_traps(struct vgic_v3_cpu_if *cpu_if);
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void __vgic_v3_save_aprs(struct vgic_v3_cpu_if *cpu_if);
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void __vgic_v3_restore_vmcr_aprs(struct vgic_v3_cpu_if *cpu_if);
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int __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu);
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/* GICv5 */
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void __vgic_v5_save_apr(struct vgic_v5_cpu_if *cpu_if);
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void __vgic_v5_restore_vmcr_apr(struct vgic_v5_cpu_if *cpu_if);
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/* No hypercalls for the following */
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void __vgic_v5_save_ppi_state(struct vgic_v5_cpu_if *cpu_if);
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void __vgic_v5_restore_ppi_state(struct vgic_v5_cpu_if *cpu_if);
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void __vgic_v5_save_state(struct vgic_v5_cpu_if *cpu_if);
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void __vgic_v5_restore_state(struct vgic_v5_cpu_if *cpu_if);
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#ifdef __KVM_NVHE_HYPERVISOR__
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void __timer_enable_traps(struct kvm_vcpu *vcpu);
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void __timer_disable_traps(struct kvm_vcpu *vcpu);
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#endif
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#ifdef __KVM_NVHE_HYPERVISOR__
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void __sysreg_save_state_nvhe(struct kvm_cpu_context *ctxt);
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void __sysreg_restore_state_nvhe(struct kvm_cpu_context *ctxt);
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#else
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void __vcpu_load_switch_sysregs(struct kvm_vcpu *vcpu);
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void __vcpu_put_switch_sysregs(struct kvm_vcpu *vcpu);
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void sysreg_save_host_state_vhe(struct kvm_cpu_context *ctxt);
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void sysreg_restore_host_state_vhe(struct kvm_cpu_context *ctxt);
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void sysreg_save_guest_state_vhe(struct kvm_cpu_context *ctxt);
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void sysreg_restore_guest_state_vhe(struct kvm_cpu_context *ctxt);
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#endif
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void __debug_switch_to_guest(struct kvm_vcpu *vcpu);
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void __debug_switch_to_host(struct kvm_vcpu *vcpu);
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#ifdef __KVM_NVHE_HYPERVISOR__
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void __debug_save_host_buffers_nvhe(struct kvm_vcpu *vcpu);
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void __debug_restore_host_buffers_nvhe(struct kvm_vcpu *vcpu);
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#endif
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void __fpsimd_save_state(struct user_fpsimd_state *fp_regs);
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void __fpsimd_restore_state(struct user_fpsimd_state *fp_regs);
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void __sve_save_state(void *sve_pffr, u32 *fpsr, int save_ffr);
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void __sve_restore_state(void *sve_pffr, u32 *fpsr, int restore_ffr);
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u64 __guest_enter(struct kvm_vcpu *vcpu);
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bool kvm_host_psci_handler(struct kvm_cpu_context *host_ctxt, u32 func_id);
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#ifdef __KVM_NVHE_HYPERVISOR__
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void __noreturn __hyp_do_panic(struct kvm_cpu_context *host_ctxt, u64 spsr,
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u64 elr, u64 par);
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#endif
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#ifdef __KVM_NVHE_HYPERVISOR__
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void __pkvm_init_switch_pgd(phys_addr_t pgd, unsigned long sp,
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void (*fn)(void));
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int __pkvm_init(phys_addr_t phys, unsigned long size, unsigned long *per_cpu_base, u32 hyp_va_bits);
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void __noreturn __host_enter(struct kvm_cpu_context *host_ctxt);
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#endif
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extern u64 kvm_nvhe_sym(id_aa64pfr0_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64pfr1_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64pfr2_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64isar0_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64isar1_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64isar2_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64mmfr0_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64mmfr1_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64mmfr2_el1_sys_val);
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extern u64 kvm_nvhe_sym(id_aa64smfr0_el1_sys_val);
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extern unsigned long kvm_nvhe_sym(__icache_flags);
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extern unsigned int kvm_nvhe_sym(kvm_arm_vmid_bits);
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extern unsigned int kvm_nvhe_sym(kvm_host_sve_max_vl);
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extern unsigned long kvm_nvhe_sym(hyp_nr_cpus);
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#endif /* __ARM64_KVM_HYP_H__ */
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