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GICv5 supports up to 128 PPIs, which would introduce a large amount of overhead if all of them were actively tracked. Rather than keeping track of all 128 potential PPIs, we instead only consider the set of architected PPIs (the first 64). Moreover, we further reduce that set by only exposing a subset of the PPIs to a guest. In practice, this means that only 4 PPIs are typically exposed to a guest - the SW_PPI, PMUIRQ, and the timers. When folding the PPI state, changed bits in the active or pending were used to choose which state to sync back. However, this breaks badly for Edge interrupts when exiting the guest before it has consumed the edge. There is no change in pending state detected, and the edge is lost forever. Given the reduced set of PPIs exposed to the guest, and the issues around tracking the edges, drop the tracking of changed state, and instead iterate over the limited subset of PPIs exposed to the guest directly. This change drops the second copy of the PPI pending state used for detecting edges in the pending state, and reworks vgic_v5_fold_ppi_state() to iterate over the VM's PPI mask instead. Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Link: https://patch.msgid.link/20260401162152.932243-1-sascha.bischoff@arm.com Signed-off-by: Marc Zyngier <maz@kernel.org>
167 lines
6.2 KiB
C
167 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2025, 2026 - Arm Ltd
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*/
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#include <linux/irqchip/arm-gic-v5.h>
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#include <asm/kvm_hyp.h>
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void __vgic_v5_save_apr(struct vgic_v5_cpu_if *cpu_if)
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{
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cpu_if->vgic_apr = read_sysreg_s(SYS_ICH_APR_EL2);
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}
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static void __vgic_v5_compat_mode_disable(void)
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{
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sysreg_clear_set_s(SYS_ICH_VCTLR_EL2, ICH_VCTLR_EL2_V3, 0);
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isb();
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}
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void __vgic_v5_restore_vmcr_apr(struct vgic_v5_cpu_if *cpu_if)
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{
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__vgic_v5_compat_mode_disable();
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write_sysreg_s(cpu_if->vgic_vmcr, SYS_ICH_VMCR_EL2);
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write_sysreg_s(cpu_if->vgic_apr, SYS_ICH_APR_EL2);
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}
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void __vgic_v5_save_ppi_state(struct vgic_v5_cpu_if *cpu_if)
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{
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/*
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* The following code assumes that the bitmap storage that we have for
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* PPIs is either 64 (architected PPIs, only) or 128 bits (architected &
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* impdef PPIs).
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*/
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BUILD_BUG_ON(VGIC_V5_NR_PRIVATE_IRQS % 64);
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bitmap_write(host_data_ptr(vgic_v5_ppi_state)->activer_exit,
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read_sysreg_s(SYS_ICH_PPI_ACTIVER0_EL2), 0, 64);
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bitmap_write(host_data_ptr(vgic_v5_ppi_state)->pendr,
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read_sysreg_s(SYS_ICH_PPI_PENDR0_EL2), 0, 64);
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cpu_if->vgic_ppi_priorityr[0] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR0_EL2);
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cpu_if->vgic_ppi_priorityr[1] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR1_EL2);
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cpu_if->vgic_ppi_priorityr[2] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR2_EL2);
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cpu_if->vgic_ppi_priorityr[3] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR3_EL2);
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cpu_if->vgic_ppi_priorityr[4] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR4_EL2);
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cpu_if->vgic_ppi_priorityr[5] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR5_EL2);
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cpu_if->vgic_ppi_priorityr[6] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR6_EL2);
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cpu_if->vgic_ppi_priorityr[7] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR7_EL2);
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if (VGIC_V5_NR_PRIVATE_IRQS == 128) {
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bitmap_write(host_data_ptr(vgic_v5_ppi_state)->activer_exit,
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read_sysreg_s(SYS_ICH_PPI_ACTIVER1_EL2), 64, 64);
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bitmap_write(host_data_ptr(vgic_v5_ppi_state)->pendr,
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read_sysreg_s(SYS_ICH_PPI_PENDR1_EL2), 64, 64);
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cpu_if->vgic_ppi_priorityr[8] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR8_EL2);
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cpu_if->vgic_ppi_priorityr[9] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR9_EL2);
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cpu_if->vgic_ppi_priorityr[10] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR10_EL2);
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cpu_if->vgic_ppi_priorityr[11] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR11_EL2);
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cpu_if->vgic_ppi_priorityr[12] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR12_EL2);
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cpu_if->vgic_ppi_priorityr[13] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR13_EL2);
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cpu_if->vgic_ppi_priorityr[14] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR14_EL2);
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cpu_if->vgic_ppi_priorityr[15] = read_sysreg_s(SYS_ICH_PPI_PRIORITYR15_EL2);
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}
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/* Now that we are done, disable DVI */
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write_sysreg_s(0, SYS_ICH_PPI_DVIR0_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_DVIR1_EL2);
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}
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void __vgic_v5_restore_ppi_state(struct vgic_v5_cpu_if *cpu_if)
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{
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DECLARE_BITMAP(pendr, VGIC_V5_NR_PRIVATE_IRQS);
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/* We assume 64 or 128 PPIs - see above comment */
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BUILD_BUG_ON(VGIC_V5_NR_PRIVATE_IRQS % 64);
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/* Enable DVI so that the guest's interrupt config takes over */
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write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_dvir, 0, 64),
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SYS_ICH_PPI_DVIR0_EL2);
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write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_activer, 0, 64),
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SYS_ICH_PPI_ACTIVER0_EL2);
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write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_enabler, 0, 64),
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SYS_ICH_PPI_ENABLER0_EL2);
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/* Update the pending state of the NON-DVI'd PPIs, only */
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bitmap_andnot(pendr, host_data_ptr(vgic_v5_ppi_state)->pendr,
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cpu_if->vgic_ppi_dvir, VGIC_V5_NR_PRIVATE_IRQS);
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write_sysreg_s(bitmap_read(pendr, 0, 64), SYS_ICH_PPI_PENDR0_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[0],
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SYS_ICH_PPI_PRIORITYR0_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[1],
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SYS_ICH_PPI_PRIORITYR1_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[2],
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SYS_ICH_PPI_PRIORITYR2_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[3],
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SYS_ICH_PPI_PRIORITYR3_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[4],
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SYS_ICH_PPI_PRIORITYR4_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[5],
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SYS_ICH_PPI_PRIORITYR5_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[6],
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SYS_ICH_PPI_PRIORITYR6_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[7],
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SYS_ICH_PPI_PRIORITYR7_EL2);
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if (VGIC_V5_NR_PRIVATE_IRQS == 128) {
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/* Enable DVI so that the guest's interrupt config takes over */
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write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_dvir, 64, 64),
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SYS_ICH_PPI_DVIR1_EL2);
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write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_activer, 64, 64),
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SYS_ICH_PPI_ACTIVER1_EL2);
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write_sysreg_s(bitmap_read(cpu_if->vgic_ppi_enabler, 64, 64),
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SYS_ICH_PPI_ENABLER1_EL2);
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write_sysreg_s(bitmap_read(pendr, 64, 64),
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SYS_ICH_PPI_PENDR1_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[8],
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SYS_ICH_PPI_PRIORITYR8_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[9],
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SYS_ICH_PPI_PRIORITYR9_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[10],
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SYS_ICH_PPI_PRIORITYR10_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[11],
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SYS_ICH_PPI_PRIORITYR11_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[12],
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SYS_ICH_PPI_PRIORITYR12_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[13],
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SYS_ICH_PPI_PRIORITYR13_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[14],
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SYS_ICH_PPI_PRIORITYR14_EL2);
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write_sysreg_s(cpu_if->vgic_ppi_priorityr[15],
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SYS_ICH_PPI_PRIORITYR15_EL2);
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} else {
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write_sysreg_s(0, SYS_ICH_PPI_DVIR1_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_ACTIVER1_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_ENABLER1_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_PENDR1_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR8_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR9_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR10_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR11_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR12_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR13_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR14_EL2);
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write_sysreg_s(0, SYS_ICH_PPI_PRIORITYR15_EL2);
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}
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}
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void __vgic_v5_save_state(struct vgic_v5_cpu_if *cpu_if)
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{
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cpu_if->vgic_vmcr = read_sysreg_s(SYS_ICH_VMCR_EL2);
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cpu_if->vgic_icsr = read_sysreg_s(SYS_ICC_ICSR_EL1);
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}
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void __vgic_v5_restore_state(struct vgic_v5_cpu_if *cpu_if)
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{
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write_sysreg_s(cpu_if->vgic_icsr, SYS_ICC_ICSR_EL1);
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}
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