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15bd4a67e9
GSC FW is loaded by submitting a dedicated command via the GSC engine.
The memory area used for loading the FW is then re-purposed as local
memory for the GSC itself, so we use a separate allocation instead of
using the one where we keep the firmware stored for reload.
The GSC is not reset as part of GT reset, so we only need to load it on
first boot and S3/S4 exit.
v2: use REG_* for register fields definitions (Rodrigo), move to WQ
immediately
v3: mark worker function as static
Bspec: 63347, 65346
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221208200521.2928378-4-daniele.ceraolospurio@intel.com
138 lines
3.0 KiB
C
138 lines
3.0 KiB
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#include <linux/types.h>
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#include "gt/intel_gt.h"
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#include "intel_gsc_uc.h"
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#include "intel_gsc_fw.h"
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#include "i915_drv.h"
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static void gsc_work(struct work_struct *work)
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{
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struct intel_gsc_uc *gsc = container_of(work, typeof(*gsc), work);
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struct intel_gt *gt = gsc_uc_to_gt(gsc);
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intel_wakeref_t wakeref;
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with_intel_runtime_pm(gt->uncore->rpm, wakeref)
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intel_gsc_uc_fw_upload(gsc);
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}
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static bool gsc_engine_supported(struct intel_gt *gt)
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{
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intel_engine_mask_t mask;
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/*
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* We reach here from i915_driver_early_probe for the primary GT before
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* its engine mask is set, so we use the device info engine mask for it.
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* For other GTs we expect the GT-specific mask to be set before we
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* call this function.
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*/
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GEM_BUG_ON(!gt_is_root(gt) && !gt->info.engine_mask);
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if (gt_is_root(gt))
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mask = RUNTIME_INFO(gt->i915)->platform_engine_mask;
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else
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mask = gt->info.engine_mask;
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return __HAS_ENGINE(mask, GSC0);
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}
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void intel_gsc_uc_init_early(struct intel_gsc_uc *gsc)
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{
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intel_uc_fw_init_early(&gsc->fw, INTEL_UC_FW_TYPE_GSC);
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INIT_WORK(&gsc->work, gsc_work);
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/* we can arrive here from i915_driver_early_probe for primary
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* GT with it being not fully setup hence check device info's
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* engine mask
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*/
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if (!gsc_engine_supported(gsc_uc_to_gt(gsc))) {
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intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_NOT_SUPPORTED);
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return;
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}
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}
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int intel_gsc_uc_init(struct intel_gsc_uc *gsc)
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{
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static struct lock_class_key gsc_lock;
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struct intel_gt *gt = gsc_uc_to_gt(gsc);
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struct drm_i915_private *i915 = gt->i915;
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struct intel_engine_cs *engine = gt->engine[GSC0];
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struct intel_context *ce;
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struct i915_vma *vma;
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int err;
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err = intel_uc_fw_init(&gsc->fw);
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if (err)
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goto out;
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vma = intel_guc_allocate_vma(>->uc.guc, SZ_8M);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto out_fw;
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}
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gsc->local = vma;
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ce = intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
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I915_GEM_HWS_GSC_ADDR,
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&gsc_lock, "gsc_context");
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if (IS_ERR(ce)) {
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drm_err(>->i915->drm,
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"failed to create GSC CS ctx for FW communication\n");
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err = PTR_ERR(ce);
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goto out_vma;
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}
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gsc->ce = ce;
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intel_uc_fw_change_status(&gsc->fw, INTEL_UC_FIRMWARE_LOADABLE);
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return 0;
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out_vma:
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i915_vma_unpin_and_release(&gsc->local, 0);
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out_fw:
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intel_uc_fw_fini(&gsc->fw);
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out:
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i915_probe_error(i915, "failed with %d\n", err);
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return err;
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}
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void intel_gsc_uc_fini(struct intel_gsc_uc *gsc)
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{
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if (!intel_uc_fw_is_loadable(&gsc->fw))
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return;
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flush_work(&gsc->work);
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if (gsc->ce)
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intel_engine_destroy_pinned_context(fetch_and_zero(&gsc->ce));
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i915_vma_unpin_and_release(&gsc->local, 0);
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intel_uc_fw_fini(&gsc->fw);
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}
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void intel_gsc_uc_suspend(struct intel_gsc_uc *gsc)
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{
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if (!intel_uc_fw_is_loadable(&gsc->fw))
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return;
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flush_work(&gsc->work);
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}
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void intel_gsc_uc_load_start(struct intel_gsc_uc *gsc)
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{
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if (!intel_uc_fw_is_loadable(&gsc->fw))
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return;
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if (intel_gsc_uc_fw_init_done(gsc))
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return;
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queue_work(system_unbound_wq, &gsc->work);
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}
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