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b0ac1b42db
GuC loading can take longer than it is supposed to for various reasons. So add in the code to cope with that and to report it when it happens. There are also many different reasons why GuC loading can fail, so add in the code for checking for those and for reporting issues in a meaningful manner rather than just hitting a timeout and saying 'fail: status = %x'. Also, remove the 'FIXME' comment about an i915 bug that has never been applicable to Xe! v2: Actually report the requested and granted frequencies rather than showing granted twice (review feedback from Badal). v3: Locally code all the timeout and end condition handling because a helper function is not allowed (review feedback from Lucas/Rodrigo). v4: Add more documentation comments and rename a define to add units (review feedback from Lucas). v5: Fix copy/paste error in xe_mmio_wait32_not (review feedback from Lucas) and rebase (no more return value from guc_wait_ucode). Signed-off-by: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240518043700.3264362-3-John.C.Harrison@Intel.com
42 lines
1.3 KiB
C
42 lines
1.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021-2023 Intel Corporation
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*/
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#ifndef _XE_MMIO_H_
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#define _XE_MMIO_H_
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#include "xe_gt_types.h"
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struct xe_device;
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struct xe_reg;
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#define LMEM_BAR 2
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int xe_mmio_init(struct xe_device *xe);
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int xe_mmio_probe_tiles(struct xe_device *xe);
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u8 xe_mmio_read8(struct xe_gt *gt, struct xe_reg reg);
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u16 xe_mmio_read16(struct xe_gt *gt, struct xe_reg reg);
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void xe_mmio_write32(struct xe_gt *gt, struct xe_reg reg, u32 val);
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u32 xe_mmio_read32(struct xe_gt *gt, struct xe_reg reg);
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u32 xe_mmio_rmw32(struct xe_gt *gt, struct xe_reg reg, u32 clr, u32 set);
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int xe_mmio_write32_and_verify(struct xe_gt *gt, struct xe_reg reg, u32 val, u32 mask, u32 eval);
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bool xe_mmio_in_range(const struct xe_gt *gt, const struct xe_mmio_range *range, struct xe_reg reg);
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int xe_mmio_probe_vram(struct xe_device *xe);
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u64 xe_mmio_read64_2x32(struct xe_gt *gt, struct xe_reg reg);
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int xe_mmio_wait32(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
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u32 *out_val, bool atomic);
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int xe_mmio_wait32_not(struct xe_gt *gt, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
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u32 *out_val, bool atomic);
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static inline u32 xe_mmio_adjusted_addr(const struct xe_gt *gt, u32 addr)
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{
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if (addr < gt->mmio.adj_limit)
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addr += gt->mmio.adj_offset;
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return addr;
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}
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#endif
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