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Add device tree bindings for Microchip's CoreSPI controller. CoreSPI is a "soft" IP core intended for FPGA implementations. Its configurations are set in Libero. These properties represent non-discoverable configurations determined by Verilog parameters to the IP. Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251114104545.284765-3-prajna.rajendrakumar@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>