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linux/Documentation
Prajna Rajendra Kumar 8ce9a2ed15 spi: dt-binding: document Microchip CoreSPI
Add device tree bindings for Microchip's CoreSPI controller.

CoreSPI is a "soft" IP core intended for FPGA implementations. Its
configurations are set in Libero. These properties represent
non-discoverable configurations determined by Verilog parameters to the
IP.

Signed-off-by: Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251114104545.284765-3-prajna.rajendrakumar@microchip.com
Signed-off-by: Mark Brown <broonie@kernel.org>
2025-11-14 13:54:42 +00:00
..
2025-10-04 15:47:24 +02:00
2025-09-21 16:35:57 -06:00
2025-09-16 10:00:57 -06:00
2025-09-09 13:37:16 -06:00