Files
linux/drivers/gpu/drm
Jani Nikula 078397bbad drm/i915/dp: use 128b/132b TPS2 for UHBR+ link rates
128b/132b channel encoding has separate TPS1 and TPS2, although the DPCD
register values coincide with 8b/10b TPS1 and TPS2 values. Use 128b/132b
TPS2 for channel equalization.

v2: Use intel_dp_is_uhbr

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> # v1
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/723b29223dc570c8b63c3c6fe5fb772d9db06c0d.1631191763.git.jani.nikula@intel.com
2021-09-20 18:46:05 +03:00
..
2021-08-10 20:14:01 +02:00
2021-08-10 20:14:01 +02:00
2021-08-10 20:14:01 +02:00
2021-08-10 20:14:01 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-10 20:14:01 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-05-17 21:19:48 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-19 09:02:55 +09:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-08-10 20:14:01 +02:00
2021-08-02 10:19:43 +02:00
2021-07-05 08:54:44 +02:00