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Currently, users of Mediatek UFOe (Unified Frame Optimization engine) DT bindings set mediatek,gce-client-reg node property, which is missing from the DT schema. For example, device tree arch/arm64/boot/dts/mediatek/mt8173.dtsi is causing the following dtb check error: arch/arm64/boot/dts/mediatek/mt8173-elm.dtb: ufoe@1401a000 (mediatek,mt8173-disp-ufoe): 'mediatek,gce-client-reg' does not match any of the regexes: '^pinctrl-[0-9]+$' This commit adds the missing node property in the DT schema and updates the example as well. Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250911151001.108744-7-ariel.dalessandro@collabora.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
108 lines
3.1 KiB
YAML
108 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,ufoe.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek display UFOe
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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Mediatek display UFOe stands for Unified Frame Optimization engine.
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UFOe can cut the data rate for DSI port which may lead to reduce power
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consumption.
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UFOe device node must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt8173-disp-ufoe
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- items:
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- const: mediatek,mt6795-disp-ufoe
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- const: mediatek,mt8173-disp-ufoe
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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power-domains:
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description: A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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clocks:
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items:
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- description: UFOe Clock
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Input and output ports can have multiple endpoints, each of those
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connects to either the primary, secondary, etc, display pipeline.
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: UFOE input, usually from one of the RDMA blocks.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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UFOE output to the input of the next desired component in the
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display pipeline, usually one of the available DSI blocks.
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required:
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- port@0
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- port@1
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mediatek,gce-client-reg:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: describes how to locate the GCE client register
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items:
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- items:
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- description: Phandle reference to a Mediatek GCE Mailbox
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- description:
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GCE subsys id mapping to a client defined in header
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include/dt-bindings/gce/<chip>-gce.h.
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- description: offset for the GCE register offset
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- description: size of the GCE register offset
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required:
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- compatible
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- reg
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- interrupts
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/gce/mt8173-gce.h>
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#include <dt-bindings/power/mt8173-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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ufoe@1401a000 {
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compatible = "mediatek,mt8173-disp-ufoe";
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reg = <0 0x1401a000 0 0x1000>;
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interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_UFOE>;
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mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>;
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};
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};
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