mirror of
https://github.com/torvalds/linux.git
synced 2026-04-18 06:44:00 -04:00
a0c70244e5
The current EPP, ISP and MPE schemas are largely compatible with Tegra114+, requiring only minor adjustments. Additionally, the TSEC schema for the Security engine, which is available from Tegra114 onwards, is included. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
69 lines
1.4 KiB
YAML
69 lines
1.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: NVIDIA Tegra Security co-processor
|
|
|
|
maintainers:
|
|
- Svyatoslav Ryhel <clamor95@gmail.com>
|
|
- Thierry Reding <thierry.reding@gmail.com>
|
|
|
|
description: Tegra Security co-processor, an embedded security processor used
|
|
mainly to manage the HDCP encryption and keys on the HDMI link.
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- enum:
|
|
- nvidia,tegra114-tsec
|
|
- nvidia,tegra124-tsec
|
|
- nvidia,tegra210-tsec
|
|
|
|
- items:
|
|
- const: nvidia,tegra132-tsec
|
|
- const: nvidia,tegra124-tsec
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
resets:
|
|
maxItems: 1
|
|
|
|
iommus:
|
|
maxItems: 1
|
|
|
|
operating-points-v2: true
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
additionalProperties: false
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- clocks
|
|
- resets
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/tegra114-car.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
tsec@54500000 {
|
|
compatible = "nvidia,tegra114-tsec";
|
|
reg = <0x54500000 0x00040000>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA114_CLK_TSEC>;
|
|
resets = <&tegra_car TEGRA114_CLK_TSEC>;
|
|
};
|