mirror of
https://github.com/torvalds/linux.git
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0f048c878e
Pull SoC dt updates from Arnd Bergmann:
"There are five sets of new SoCs that get added in existing families,
all of them being either upgrades or cut-down versions of the older
chips:
- Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation
of high-end workstations and laptops from Apple. Linux has been
working on these for a while but stil requires patches.
- Axis Artpec8 is an Armv8 chip based on Samsung Exynos design,
unlike the earlier Armv7 Artpec6 from the same company that was
part of a separate family of chips.
- NXP i.MX91 is a cut-down version of i.MX93, using only a single
Cortex-A55 core.
- Qualcomm Lemans Auto is a variant of the Lemans SoC that was
originally merged under the sa8775p name, the differences being
mostly the firmware configuration of the platform.
- Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44),
RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial
bedded SoCs based on Cortex-A55 cores
In total, there are 65 new machines, including:
- Industrial embedded system and single-board computers based on NXP,
Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips.
- Reference boards for the newly added Renesas, Qualcomm, NXP and
Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC
- Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1
chips.
- Several Samsung phones using Qualcomm Snapdragon chips
- Set-top boxes based on Allwinner H313
- Five BMC boards using 32-bit ASpeed SoCs
- Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708
(ARMv7) SoCs
Two machines get phased out because they were available only in small
quantities but never made it into products: one STi407 based reference
board, and a Snapdragon 845 based Chromebook.
Aside from the newly added machines, a lot of work went into improving
hardware support on the existing machines and cleaning up contents for
validation"
* tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits)
arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible
arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node
ARM: dts: microchip: sam9x7: Add qspi controller
arm64: dts: qcom: Add MST pixel streams for displayport
arm64: dts: qcom: sm6350: correct DP compatibility strings
arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300: Add gpu and gmu nodes
arm64: dts: allwinner: h313: Add Amediatech X96Q
dt-bindings: arm: sunxi: Add Amediatech X96Q
arm64: dts: apple: t8015: Add SPMI node
arm64: dts: apple: t8012: Add SPMI node
arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree
arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT
dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT
arm64: dts: rockchip: update pinctrl names for Radxa E52C
arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C
arm64: dts: apple: Add J474s, J475c and J475d device trees
arm64: dts: apple: Add J414 and J416 Macbook Pro device trees
arm64: dts: apple: Add initial t6020/t6021/t6022 DTs
...
225 lines
7.3 KiB
YAML
225 lines
7.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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maintainers:
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- Thierry Reding <thierry.reding@gmail.com>
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- Jon Hunter <jonathanh@nvidia.com>
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title: NVIDIA Tegra I2C controller driver
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properties:
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compatible:
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oneOf:
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- description: Tegra20 has 4 generic I2C controller. This can support
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master and slave mode of I2C communication. The i2c-tegra driver
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only support master mode of I2C communication. Driver of I2C
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controller is only compatible with "nvidia,tegra20-i2c".
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const: nvidia,tegra20-i2c
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- description: Tegra20 has specific I2C controller called as DVC I2C
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controller. This only support master mode of I2C communication.
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Register interface/offset and interrupts handling are different than
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generic I2C controller. Driver of DVC I2C controller is only
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compatible with "nvidia,tegra20-i2c-dvc".
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const: nvidia,tegra20-i2c-dvc
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- description: |
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Tegra30 has 5 generic I2C controller. This controller is very much
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similar to Tegra20 I2C controller with additional feature: Continue
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Transfer Support. This feature helps to implement M_NO_START as per
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I2C core API transfer flags. Driver of I2C controller is compatible
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with "nvidia,tegra30-i2c" to enable the continue transfer support.
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This is also compatible with "nvidia,tegra20-i2c" without continue
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transfer support.
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items:
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- const: nvidia,tegra30-i2c
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- const: nvidia,tegra20-i2c
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- description: |
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Tegra114 has 5 generic I2C controllers. This controller is very much
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similar to Tegra30 I2C controller with some hardware modification:
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- Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
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and fast-clk. Tegra114 has only one clock source called as
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div-clk and hence clock mechanism is changed in I2C controller.
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- Tegra30/Tegra20 I2C controller has enabled per packet transfer
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by default and there is no way to disable it. Tegra114 has this
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interrupt disable by default and SW need to enable explicitly.
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Due to above changes, Tegra114 I2C driver makes incompatible with
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previous hardware driver. Hence, Tegra114 I2C controller is
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compatible with "nvidia,tegra114-i2c".
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const: nvidia,tegra114-i2c
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- description: |
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Tegra124 has 6 generic I2C controllers. These controllers are very
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similar to those found on Tegra114 but also contain several hardware
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improvements and new registers.
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const: nvidia,tegra124-i2c
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- description: |
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Tegra210 has 6 generic I2C controllers. These controllers are very
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similar to those found on Tegra124.
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items:
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- const: nvidia,tegra210-i2c
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- const: nvidia,tegra124-i2c
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- description: |
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Tegra210 has one I2C controller that is on host1x bus and is part of
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the VE power domain and typically used for camera use-cases. This VI
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I2C controller is mostly compatible with the programming model of
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the regular I2C controllers with a few exceptions. The I2C registers
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start at an offset of 0xc00 (instead of 0), registers are 16 bytes
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apart (rather than 4) and the controller does not support slave
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mode.
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const: nvidia,tegra210-i2c-vi
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- description: |
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Tegra186 has 9 generic I2C controllers, two of which are in the AON
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(always-on) partition of the SoC. All of these controllers are very
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similar to those found on Tegra210.
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const: nvidia,tegra186-i2c
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- description: |
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Tegra194 has 8 generic I2C controllers, two of which are in the AON
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(always-on) partition of the SoC. All of these controllers are very
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similar to those found on Tegra186. However, these controllers have
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support for 64 KiB transactions whereas earlier chips supported no
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more than 4 KiB per transactions.
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const: nvidia,tegra194-i2c
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- description: |
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Tegra256 has 8 generic I2C controllers. The controllers are similar to
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the previous generations, but have a different parent clock and hence
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the timing parameters are configured differently.
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const: nvidia,tegra256-i2c
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- description:
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Tegra264 has 17 generic I2C controllers, two of which are in the AON
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(always-on) partition of the SoC. In addition to the features from
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Tegra194, a SW mutex register is added to support use of the same I2C
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instance across multiple firmwares.
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const: nvidia,tegra264-i2c
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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resets:
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items:
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- description:
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Module reset. This property is optional for controllers in Tegra194,
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Tegra234 etc where an internal software reset is available as an
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alternative.
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reset-names:
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items:
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- const: i2c
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power-domains:
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maxItems: 1
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dmas:
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items:
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- description: DMA channel for the reception FIFO
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- description: DMA channel for the transmission FIFO
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dma-names:
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items:
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- const: rx
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- const: tx
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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allOf:
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- $ref: /schemas/i2c/i2c-controller.yaml
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra20-i2c
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- nvidia,tegra30-i2c
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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items:
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- const: div-clk
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- const: fast-clk
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- if:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra114-i2c
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- nvidia,tegra210-i2c
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: div-clk
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- if:
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properties:
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compatible:
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contains:
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const: nvidia,tegra210-i2c-vi
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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items:
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- const: div-clk
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- const: slow
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power-domains:
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items:
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- description: phandle to the VENC power domain
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else:
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properties:
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power-domains: false
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- nvidia,tegra194-i2c
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- nvidia,tegra256-i2c
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- nvidia,tegra264-i2c
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then:
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required:
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- resets
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- reset-names
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unevaluatedProperties: false
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examples:
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- |
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i2c@7000c000 {
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compatible = "nvidia,tegra20-i2c";
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reg = <0x7000c000 0x100>;
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interrupts = <0 38 0x04>;
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clocks = <&tegra_car 12>, <&tegra_car 124>;
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clock-names = "div-clk", "fast-clk";
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resets = <&tegra_car 12>;
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reset-names = "i2c";
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dmas = <&apbdma 16>, <&apbdma 16>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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