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7c0b084c04
Add device tree bindings for the Video Input Port. Video Input Port (VIP) can be found on devices such as DRA7xx and provides a parallel interface to a video source such as a sensor or TV decoder. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Dale Farnsworth <dale@farnsworth.org> Signed-off-by: Benoit Parrot <bparrot@ti.com> Signed-off-by: Sukrut Bellary <sbellary@baylibre.com> Signed-off-by: Yemike Abhilash Chandra <y-abhilashchandra@ti.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
153 lines
4.1 KiB
YAML
153 lines
4.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/ti,vip.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments DRA7x Video Input Port (VIP)
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maintainers:
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- Yemike Abhilash Chandra <y-abhilashchandra@ti.com>
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description: |-
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Video Input Port (VIP) can be found on devices such as DRA7xx and
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provides the system interface and the processing capability to
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connect parallel image-sensor as well as BT.656/1120 capable encoder
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chip to DRA7x device.
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Each VIP instance supports 2 independently configurable external
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video input capture slices (Slice 0 and Slice 1) each providing
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up to two video input ports (Port A and Port B).
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properties:
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compatible:
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enum:
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- ti,dra7-vip
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: IRQ index 0 is used for Slice0 interrupts
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- description: IRQ index 1 is used for Slice1 interrupts
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ti,ctrl-module:
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description:
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Reference to the device control module that provides clock-edge
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inversion control for VIP ports. These controls allow the
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VIP to sample pixel data on the correct clock edge.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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items:
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- description: phandle to device control module
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- description: offset to the CTRL_CORE_SMA_SW_1 register
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- description: Bit field to slice 0 port A
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- description: Bit field to slice 0 port B
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- description: Bit field to slice 1 port A
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- description: Bit field to slice 1 port B
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maxItems: 1
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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patternProperties:
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'^port@[0-3]$':
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description: |
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Each VIP instance supports 2 independently configurable external video
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input capture slices (Slice 0 and Slice 1) each providing up to two video
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input ports (Port A and Port B). These ports represent the following
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port@0 -> Slice 0 Port A
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port@1 -> Slice 0 Port B
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port@2 -> Slice 1 Port A
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port@3 -> Slice 1 Port B
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properties:
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endpoint:
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$ref: /schemas/media/video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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bus-width:
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enum: [8, 16, 24]
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default: 8
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required:
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- compatible
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- reg
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- interrupts
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- ti,ctrl-module
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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video@48970000 {
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compatible = "ti,dra7-vip";
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reg = <0x48970000 0x1000>;
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interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
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ti,ctrl-module = <&scm_conf 0x534 0x0 0x2 0x1 0x3>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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vin1a: port@0 {
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reg = <0>;
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vin1a_ep: endpoint {
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remote-endpoint = <&camera1>;
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hsync-active = <1>;
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vsync-active = <1>;
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pclk-sample = <0>;
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bus-width = <8>;
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};
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};
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vin1b: port@1 {
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reg = <1>;
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vin1b_ep: endpoint {
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remote-endpoint = <&camera2>;
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hsync-active = <1>;
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vsync-active = <1>;
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pclk-sample = <0>;
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bus-width = <8>;
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};
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};
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vin2a: port@2 {
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reg = <2>;
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vin2a_ep: endpoint {
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remote-endpoint = <&camera3>;
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hsync-active = <1>;
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vsync-active = <1>;
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pclk-sample = <0>;
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bus-width = <16>;
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};
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};
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vin2b: port@3 {
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reg = <3>;
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vin2b_ep: endpoint {
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remote-endpoint = <&camera4>;
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hsync-active = <1>;
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vsync-active = <1>;
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pclk-sample = <0>;
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bus-width = <8>;
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};
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};
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};
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};
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...
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