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b445c14ac7
Add SCU interrupt controller compatible strings for the AST2700 SoC: scu-ic0 to 3. This extends the MFD binding to support AST2700-based platforms. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250831021438.976893-3-ryan_chen@aspeedtech.com Signed-off-by: Lee Jones <lee@kernel.org>
167 lines
4.0 KiB
YAML
167 lines
4.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Aspeed System Control Unit
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description:
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The Aspeed System Control Unit manages the global behaviour of the SoC,
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configuring elements such as clocks, pinmux, and reset.
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In AST2700 SOC which has two soc connection, each soc have its own scu
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register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.
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maintainers:
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- Joel Stanley <joel@jms.id.au>
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- Andrew Jeffery <andrew@aj.id.au>
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properties:
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compatible:
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items:
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- enum:
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- aspeed,ast2400-scu
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- aspeed,ast2500-scu
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- aspeed,ast2600-scu
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- aspeed,ast2700-scu0
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- aspeed,ast2700-scu1
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- const: syscon
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- const: simple-mfd
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reg:
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maxItems: 1
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ranges: true
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'#address-cells':
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minimum: 1
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maximum: 2
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'#size-cells':
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const: 1
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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patternProperties:
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'^p2a-control@[0-9a-f]+$':
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description: >
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PCI-to-AHB Bridge Control
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The bridge is available on platforms with the VGA enabled on the Aspeed
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device. In this case, the host has access to a 64KiB window into all of
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the BMC's memory. The BMC can disable this bridge. If the bridge is
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enabled, the host has read access to all the regions of memory, however
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the host only has read and write access depending on a register
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controlled by the BMC.
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type: object
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additionalProperties: false
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properties:
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compatible:
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enum:
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- aspeed,ast2400-p2a-ctrl
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- aspeed,ast2500-p2a-ctrl
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reg:
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maxItems: 1
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memory-region:
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maxItems: 1
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description:
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A reserved_memory region to be used for the PCI to AHB mapping
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required:
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- compatible
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- reg
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'^pinctrl(@[0-9a-f]+)?$':
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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enum:
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- aspeed,ast2400-pinctrl
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- aspeed,ast2500-pinctrl
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- aspeed,ast2600-pinctrl
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required:
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- compatible
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'^interrupt-controller@[0-9a-f]+$':
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type: object
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additionalProperties: true
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properties:
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compatible:
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contains:
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enum:
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- aspeed,ast2500-scu-ic
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- aspeed,ast2600-scu-ic0
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- aspeed,ast2600-scu-ic1
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- aspeed,ast2700-scu-ic0
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- aspeed,ast2700-scu-ic1
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- aspeed,ast2700-scu-ic2
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- aspeed,ast2700-scu-ic3
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'^silicon-id@[0-9a-f]+$':
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description: Unique hardware silicon identifiers within the SoC
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type: object
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additionalProperties: false
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properties:
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compatible:
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items:
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- enum:
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- aspeed,ast2400-silicon-id
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- aspeed,ast2500-silicon-id
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- aspeed,ast2600-silicon-id
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- aspeed,ast2700-silicon-id
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- const: aspeed,silicon-id
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reg:
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description:
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The reg should be the unique silicon id register, and not backwards
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compatible one in eg. the 2600.
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minItems: 1
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items:
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- description: silicon id information registers
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- description: unique chip id registers
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required:
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- compatible
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- reg
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- ranges
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- '#address-cells'
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- '#size-cells'
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- '#clock-cells'
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- '#reset-cells'
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additionalProperties: false
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examples:
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- |
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syscon@1e6e2000 {
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compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
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reg = <0x1e6e2000 0x1a8>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x1e6e2000 0x1000>;
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p2a-control@2c {
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compatible = "aspeed,ast2400-p2a-ctrl";
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reg = <0x2c 0x4>;
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};
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silicon-id@7c {
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compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
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reg = <0x7c 0x4>, <0x150 0x8>;
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};
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};
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...
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