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Document the bindings for CIX Sky1 PCIe Controller configured in Root Complex mode with five Root Ports. The controller supports 4 INTx, MSI and MSI-X interrupts with the help of the ARM GICv3 interrupt controller. Signed-off-by: Hans Zhang <hans.zhang@cixtech.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251108140305.1120117-6-hans.zhang@cixtech.com
84 lines
2.4 KiB
YAML
84 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: CIX Sky1 PCIe Root Complex
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maintainers:
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- Hans Zhang <hans.zhang@cixtech.com>
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description:
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PCIe root complex controller based on the Cadence PCIe core.
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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properties:
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compatible:
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const: cix,sky1-pcie-host
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reg:
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items:
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- description: PCIe controller registers.
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- description: ECAM registers.
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- description: Remote CIX System Unit strap registers.
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- description: Remote CIX System Unit status registers.
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- description: Region for sending messages registers.
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reg-names:
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items:
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- const: reg
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- const: cfg
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- const: rcsu_strap
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- const: rcsu_status
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- const: msg
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ranges:
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maxItems: 3
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required:
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- compatible
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- ranges
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- bus-range
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- device_type
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- interrupt-map
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- interrupt-map-mask
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- msi-map
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@a010000 {
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compatible = "cix,sky1-pcie-host";
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reg = <0x00 0x0a010000 0x00 0x10000>,
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<0x00 0x2c000000 0x00 0x4000000>,
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<0x00 0x0a000300 0x00 0x100>,
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<0x00 0x0a000400 0x00 0x100>,
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<0x00 0x60000000 0x00 0x00100000>;
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reg-names = "reg", "cfg", "rcsu_strap", "rcsu_status", "msg";
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ranges = <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x00100000>,
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<0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1fe00000>,
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<0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0xc0 0xff>;
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device_type = "pci";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>,
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<0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>,
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<0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>,
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<0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>;
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msi-map = <0xc000 &gic_its 0xc000 0x4000>;
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};
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};
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