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Introduce Airoha AN7583 SoC compatible in mediatek PCIe controller binding. Similar to GEN3, the Airoha AN7583 GEN2 PCIe controller require the PBUS csr property to permit the correct functionality of the PCIe controller. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251020111121.31779-3-ansuelsmth@gmail.com
439 lines
11 KiB
YAML
439 lines
11 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/mediatek-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: PCIe controller on MediaTek SoCs
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maintainers:
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- Christian Marangi <ansuelsmth@gmail.com>
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properties:
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compatible:
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oneOf:
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- enum:
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- airoha,an7583-pcie
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- mediatek,mt2712-pcie
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- mediatek,mt7622-pcie
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- mediatek,mt7629-pcie
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- items:
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- const: airoha,en7523-pcie
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- const: mediatek,mt7622-pcie
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reg:
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maxItems: 1
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reg-names:
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enum: [ port0, port1 ]
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clocks:
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minItems: 1
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maxItems: 6
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clock-names:
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minItems: 1
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items:
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- enum: [ sys_ck0, sys_ck1 ]
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- enum: [ ahb_ck0, ahb_ck1 ]
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- enum: [ aux_ck0, aux_ck1 ]
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- enum: [ axi_ck0, axi_ck1 ]
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- enum: [ obff_ck0, obff_ck1 ]
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- enum: [ pipe_ck0, pipe_ck1 ]
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resets:
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maxItems: 1
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reset-names:
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const: pcie-rst1
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interrupts:
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maxItems: 1
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interrupt-names:
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const: pcie_irq
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phys:
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maxItems: 1
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phy-names:
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enum: [ pcie-phy0, pcie-phy1 ]
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power-domains:
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maxItems: 1
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mediatek,pbus-csr:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to pbus-csr syscon
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- description: offset of pbus-csr base address register
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- description: offset of pbus-csr base address mask register
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description:
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Phandle with two arguments to the syscon node used to detect if
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a given address is accessible on PCIe controller.
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'#interrupt-cells':
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const: 1
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interrupt-controller:
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description: Interrupt controller node for handling legacy PCI interrupts.
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type: object
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properties:
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'#address-cells':
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const: 0
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'#interrupt-cells':
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const: 1
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interrupt-controller: true
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required:
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- '#address-cells'
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- '#interrupt-cells'
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- interrupt-controller
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additionalProperties: false
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required:
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- compatible
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- reg
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- reg-names
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- ranges
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- clocks
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- clock-names
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- '#interrupt-cells'
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- interrupts
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- interrupt-names
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- interrupt-controller
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allOf:
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- $ref: /schemas/pci/pci-host-bridge.yaml#
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- if:
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properties:
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compatible:
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const: airoha,an7583-pcie
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then:
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properties:
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reg-names:
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const: port1
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clocks:
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maxItems: 1
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clock-names:
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const: sys_ck1
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phy-names:
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const: pcie-phy1
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power-domain: false
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required:
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- resets
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- reset-names
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- phys
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- phy-names
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- mediatek,pbus-csr
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- if:
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properties:
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compatible:
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const: mediatek,mt2712-pcie
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then:
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properties:
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clocks:
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minItems: 2
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maxItems: 2
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clock-names:
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minItems: 2
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maxItems: 2
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reset: false
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reset-names: false
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power-domains: false
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mediatek,pbus-csr: false
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required:
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- phys
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- phy-names
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- if:
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properties:
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compatible:
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const: mediatek,mt7622-pcie
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then:
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properties:
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clocks:
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minItems: 6
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reset: false
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reset-names: false
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phys: false
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phy-names: false
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mediatek,pbus-csr: false
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required:
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- power-domains
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- if:
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properties:
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compatible:
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const: mediatek,mt7629-pcie
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then:
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properties:
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clocks:
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minItems: 6
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reset: false
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reset-names: false
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mediatek,pbus-csr: false
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required:
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- power-domains
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- if:
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properties:
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compatible:
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contains:
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const: airoha,en7523-pcie
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then:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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maxItems: 1
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reset: false
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reset-names: false
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phys: false
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phy-names: false
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power-domain: false
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mediatek,pbus-csr: false
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unevaluatedProperties: false
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examples:
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# MT2712
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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soc_1 {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@112ff000 {
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compatible = "mediatek,mt2712-pcie";
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device_type = "pci";
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reg = <0 0x112ff000 0 0x1000>;
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reg-names = "port1";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie_irq";
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clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P1_SEL */
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<&pericfg>; /* CLK_PERI_PCIE1 */
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clock-names = "sys_ck1", "ahb_ck1";
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phys = <&u3port1 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy1";
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie@11700000 {
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compatible = "mediatek,mt2712-pcie";
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device_type = "pci";
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reg = <0 0x11700000 0 0x1000>;
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reg-names = "port0";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie_irq";
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clocks = <&topckgen>, /* CLK_TOP_PE2_MAC_P0_SEL */
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<&pericfg>; /* CLK_PERI_PCIE0 */
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clock-names = "sys_ck0", "ahb_ck0";
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phys = <&u3port0 PHY_TYPE_PCIE>;
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phy-names = "pcie-phy0";
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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<0 0 0 3 &pcie_intc0 2>,
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<0 0 0 4 &pcie_intc0 3>;
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pcie_intc0: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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# MT7622
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/mt7622-power.h>
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soc_2 {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@1a143000 {
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compatible = "mediatek,mt7622-pcie";
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device_type = "pci";
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reg = <0 0x1a143000 0 0x1000>;
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reg-names = "port0";
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "pcie_irq";
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clocks = <&pciesys>, /* CLK_PCIE_P0_MAC_EN */
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<&pciesys>, /* CLK_PCIE_P0_AHB_EN */
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<&pciesys>, /* CLK_PCIE_P0_AUX_EN */
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<&pciesys>, /* CLK_PCIE_P0_AXI_EN */
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<&pciesys>, /* CLK_PCIE_P0_OBFF_EN */
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<&pciesys>; /* CLK_PCIE_P0_PIPE_EN */
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clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
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"axi_ck0", "obff_ck0", "pipe_ck0";
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0_1 0>,
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<0 0 0 2 &pcie_intc0_1 1>,
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<0 0 0 3 &pcie_intc0_1 2>,
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<0 0 0 4 &pcie_intc0_1 3>;
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pcie_intc0_1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie@1a145000 {
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compatible = "mediatek,mt7622-pcie";
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device_type = "pci";
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reg = <0 0x1a145000 0 0x1000>;
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reg-names = "port1";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "pcie_irq";
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clocks = <&pciesys>, /* CLK_PCIE_P1_MAC_EN */
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/* designer has connect RC1 with p0_ahb clock */
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<&pciesys>, /* CLK_PCIE_P0_AHB_EN */
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<&pciesys>, /* CLK_PCIE_P1_AUX_EN */
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<&pciesys>, /* CLK_PCIE_P1_AXI_EN */
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<&pciesys>, /* CLK_PCIE_P1_OBFF_EN */
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<&pciesys>; /* CLK_PCIE_P1_PIPE_EN */
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clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
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"axi_ck1", "obff_ck1", "pipe_ck1";
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1_1 0>,
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<0 0 0 2 &pcie_intc1_1 1>,
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<0 0 0 3 &pcie_intc1_1 2>,
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<0 0 0 4 &pcie_intc1_1 3>;
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pcie_intc1_1: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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# AN7583
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/en7523-clk.h>
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soc_3 {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@1fa92000 {
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compatible = "airoha,an7583-pcie";
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device_type = "pci";
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x0 0x1fa92000 0x0 0x1670>;
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reg-names = "port1";
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clocks = <&scuclk EN7523_CLK_PCIE>;
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clock-names = "sys_ck1";
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phys = <&pciephy>;
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phy-names = "pcie-phy1";
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ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
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resets = <&scuclk>; /* AN7583_PCIE1_RST */
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reset-names = "pcie-rst1";
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mediatek,pbus-csr = <&pbus_csr 0x8 0xc>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pcie_irq";
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bus-range = <0x00 0xff>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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<0 0 0 3 &pcie_intc1 2>,
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<0 0 0 4 &pcie_intc1 3>;
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pcie_intc1_4: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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