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edf1701c86
Move IPQ8074 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing and maintenance easier. New schema is equivalent to the old one with few changes: - Adding a required compatible, which is actually redundant. - Drop the really obvious comments next to clock/reg/reset-names items. - Expecting eight MSI interrupts and one global, instead of only one, which was incomplete hardware description. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251217-dt-bindings-pci-qcom-v2-7-873721599754@oss.qualcomm.com
166 lines
4.6 KiB
YAML
166 lines
4.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/qcom,pcie-ipq8074.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm IPQ8074 PCI Express Root Complex
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Manivannan Sadhasivam <mani@kernel.org>
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properties:
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compatible:
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enum:
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- qcom,pcie-ipq8074
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reg:
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maxItems: 4
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reg-names:
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items:
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- const: dbi
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- const: elbi
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- const: parf
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- const: config
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clocks:
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maxItems: 5
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clock-names:
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items:
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- const: iface # PCIe to SysNOC BIU clock
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- const: axi_m # AXI Master clock
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- const: axi_s # AXI Slave clock
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- const: ahb
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- const: aux
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interrupts:
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maxItems: 9
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interrupt-names:
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items:
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- const: msi0
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- const: msi1
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- const: msi2
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- const: msi3
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- const: msi4
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- const: msi5
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- const: msi6
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- const: msi7
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- const: global
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resets:
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maxItems: 7
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reset-names:
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items:
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- const: pipe
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- const: sleep
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- const: sticky # Core sticky reset
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- const: axi_m # AXI master reset
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- const: axi_s # AXI slave reset
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- const: ahb
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- const: axi_m_sticky # AXI master sticky reset
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required:
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- resets
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- reset-names
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allOf:
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- $ref: qcom,pcie-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie@10000000 {
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compatible = "qcom,pcie-ipq8074";
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reg = <0x10000000 0xf1d>,
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<0x10000f20 0xa8>,
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<0x00088000 0x2000>,
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<0x10100000 0x1000>;
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reg-names = "dbi", "elbi", "parf", "config";
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ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
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<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
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device_type = "pci";
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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max-link-speed = <2>;
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#address-cells = <3>;
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#size-cells = <2>;
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clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
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<&gcc GCC_PCIE1_AXI_M_CLK>,
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<&gcc GCC_PCIE1_AXI_S_CLK>,
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<&gcc GCC_PCIE1_AHB_CLK>,
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<&gcc GCC_PCIE1_AUX_CLK>;
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clock-names = "iface",
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"axi_m",
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"axi_s",
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"ahb",
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"aux";
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 0 GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
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<0 0 0 2 &intc 0 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
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<0 0 0 3 &intc 0 GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
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<0 0 0 4 &intc 0 GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
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phys = <&pcie_qmp1>;
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phy-names = "pciephy";
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resets = <&gcc GCC_PCIE1_PIPE_ARES>,
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<&gcc GCC_PCIE1_SLEEP_ARES>,
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<&gcc GCC_PCIE1_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE1_AXI_MASTER_ARES>,
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<&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
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<&gcc GCC_PCIE1_AHB_ARES>,
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<&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
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reset-names = "pipe",
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"sleep",
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"sticky",
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"axi_m",
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"axi_s",
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"ahb",
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"axi_m_sticky";
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perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
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pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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